HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46238 )
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/xhci.asl 9 files changed, 264 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/1
diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl index 435db4d..51dd38c 100644 --- a/src/soc/intel/broadwell/acpi/adsp.asl +++ b/src/soc/intel/broadwell/acpi/adsp.asl @@ -25,11 +25,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR address and length if set in NVS - If (LNotEqual (\S8B0, Zero)) { + If (\S8B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B8A0) CreateDwordField (^RBUF, ^BAR1._BAS, B8A1) - Store (\S8B0, B8A0) - Store (\S8B1, B8A1) + B8A0 = \S8B0 + B8A1 = \S8B1 }
Return (RBUF) @@ -37,7 +37,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S8EN, 0)) { + If (\S8EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 8391482..e592d7e 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,8 +9,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, - Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -62,17 +61,16 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (_SB.CP00._PSS)
- While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf ( (DeRefOf (_SB.CP00._PSS [Local0]) [4]) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ }
Return (0) @@ -83,7 +81,7 @@ { /* Haswell ULT PL2 = 25W */ /* FIXME: update for broadwell */ - Return (Multiply (25, 8)) + Return (25 * 8)) }
/* Set Config TDP Down */ @@ -92,31 +90,31 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) }
- Store ("Set TDP Down", Debug) + Debug = "Set TDP Down"
/* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD
/* Set TAR */ - Store (TARD, TARS) + TARS = TARD
/* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN ()
/* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD)
/* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD
/* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD
Release (CTCM) Return (1) @@ -128,31 +126,31 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) }
- Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal"
/* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN
/* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN)
/* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN ()
/* Set TAR */ - Store (TARN, TARS) + TARS = TARN
/* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN
/* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN
Release (CTCM) Return (1) @@ -161,7 +159,7 @@ /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) }
/* Enable Controllable TDP to limit PL1 to requested value */ @@ -171,22 +169,22 @@ Return (0) }
- Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit"
/* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN ()
/* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1
/* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0)
/* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1
Release (CTCM) Return (1) @@ -199,19 +197,19 @@ Return (0) }
- Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit"
/* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0
/* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1
/* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0
/* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN ()
Release (CTCM) diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 3c6c5f5..1fa6a13 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -57,35 +57,35 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) + \S3U0 = 1 }
/* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) + \S3U0 = 0 }
/* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) + \S5U0 = 1 }
/* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) + \S5U0 = 0 }
/* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 }
/* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl index cfe0aed..8d4e33e 100644 --- a/src/soc/intel/broadwell/acpi/gpio.asl +++ b/src/soc/intel/broadwell/acpi/gpio.asl @@ -41,10 +41,9 @@ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
- Store (GPIO_BASE_SIZE, BLEN) - Store (GPIO_BASE_ADDRESS, BMIN) - Store (Subtract (Add (GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE), 1), BMAX) + BLEN = GPIO_BASE_SIZE + BMIN = GPIO_BASE_ADDRESS + BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE) - 1
Return (RBUF) } @@ -59,17 +58,18 @@ Method (GWAK, 1, Serialized) { // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) + Local0 = GPBS & ~1
// Local1 = BANK, Local2 = OFFSET - Divide (Arg0, 32, Local2, Local1) + Local2 = Arg0 % 32 + Local1 = Arg0 / 32
// // Set OWNER to ACPI //
// Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + Local3 = Local0 + (Local1 * 4)
// GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -78,14 +78,14 @@ }
// GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + GOWN = GOWN & ~(1 << Local2)
// // Set ROUTE to SCI //
// Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + Local3 = Local0 + 0x30 + (Local1 * 4)
// GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -94,14 +94,14 @@ }
// GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + GROU = GROU & ~(1 << Local2)
// // Set GPnCONFIG to GPIO|INPUT|INVERT //
// Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + Local3 = Local0 + 0x100 + (Arg0 * 8)
// GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) @@ -118,8 +118,8 @@ ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE }
- Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT + GMOD = 1 // GPIO + GIOS = 1 // INPUT + GINV = 1 // INVERT } } diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl index 0661ff8..1ea836d 100644 --- a/src/soc/intel/broadwell/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/acpi/irqlinks.asl @@ -8,7 +8,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 }
// Possible Resource Settings for this Link @@ -28,10 +28,10 @@ CreateWordField (RTLA, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTA - ShiftLeft (1, And (PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f)
Return (RTLA) } @@ -44,14 +44,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTA) + Local0-- + PRTA = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 }
// Possible Resource Settings for this Link @@ -87,10 +87,10 @@ CreateWordField (RTLB, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTB - ShiftLeft (1, And (PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f)
Return (RTLB) } @@ -103,14 +103,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTB) + Local0-- + PRTB = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 }
// Possible Resource Settings for this Link @@ -146,10 +146,10 @@ CreateWordField (RTLC, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTC - ShiftLeft (1, And (PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f)
Return (RTLC) } @@ -162,14 +162,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTC) + Local0-- + PRTC = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 }
// Possible Resource Settings for this Link @@ -205,10 +205,10 @@ CreateWordField (RTLD, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTD - ShiftLeft (1, And (PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f)
Return (RTLD) } @@ -221,14 +221,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTD) + Local0-- + PRTD = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTD, 0x80)) { + If PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 }
// Possible Resource Settings for this Link @@ -264,10 +264,10 @@ CreateWordField (RTLE, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTE - ShiftLeft (1, And (PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f)
Return (RTLE) } @@ -280,14 +280,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTE) + Local0-- + PRTE = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 }
// Possible Resource Settings for this Link @@ -323,10 +323,10 @@ CreateWordField (RTLF, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTF - ShiftLeft (1, And (PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f)
Return (RTLF) } @@ -339,14 +339,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTF) + Local0-- + PRTF = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 }
// Possible Resource Settings for this Link @@ -382,10 +382,10 @@ CreateWordField (RTLG, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTG - ShiftLeft (1, And (PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f)
Return (RTLG) } @@ -398,14 +398,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTG) + Local0-- + PRTG = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 }
// Possible Resource Settings for this Link @@ -441,10 +441,10 @@ CreateWordField (RTLH, 1, IRQ0)
// Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0
// Set the bit from PRTH - ShiftLeft (1, And (PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f)
Return (RTLH) } @@ -457,14 +457,14 @@ // Which bit is set? FindSetRightBit (IRQ0, Local0)
- Decrement(Local0) - Store (Local0, PRTH) + Local0-- + PRTH = Local0 }
// Status Method (_STA, 0, Serialized) { - If(And (PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 33c8dc9..9c72cae 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -68,7 +68,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -84,16 +84,16 @@ CreateDWordField (BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
- If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 }
- If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 }
- If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } }
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index 07db9f7..2c9a4d1 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -29,8 +29,8 @@ */ Method (ISWP) { - And (_SB.PCI0.LPCB.PDID, 0xfff0, Local0) - If (LEqual (Local0, 0x9cc0)) { + Local0 = _SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { Return (1) } Else { Return (0) @@ -68,7 +68,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -77,7 +77,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 218ddc3..5d12cd3 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -11,7 +11,7 @@ Method (LPD0, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1== 0) { Return }
@@ -21,11 +21,11 @@ SPCS, 32 }
- And (SPCS, 0xFFFFFFFC, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS &= 0xFFFFFFFC + Local0 = SPCS // Read back after writing
// Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones }
// Put SerialIO device in D3 state @@ -34,7 +34,7 @@ Method (LPD3, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1== 0) { Return }
@@ -44,11 +44,11 @@ SPCS, 32 }
- Or (SPCS, 0x3, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS |= 3 + Local0 = SPCS // Read back after writing
// Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones }
// Serial IO Resource Consumption for BAR1 @@ -74,67 +74,67 @@ Method (_CRS, 0, NotSerialized) { // SDMA - If (LNotEqual (\S0B1, Zero)) { + If (\S0B1 != 0) { CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B1 + B0LN = SIO_BAR_LEN }
// I2C0 - If (LNotEqual (\S1B1, Zero)) { + If (\S1B1 != 0) { CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) + B1AD = \S1B1 + B1LN = SIO_BAR_LEN }
// I2C1 - If (LNotEqual (\S2B1, Zero)) { + If (\S2B1 != 0) { CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) + B2AD = \S2B1 + B2LN = SIO_BAR_LEN }
// SPI0 - If (LNotEqual (\S3B1, Zero)) { + If (\S3B1 != 0) { CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) + B3AD = \S3B1 + B3LN = SIO_BAR_LEN }
// SPI1 - If (LNotEqual (\S4B1, Zero)) { + If (\S4B1 != 0) { CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) + B4AD = \S4B1 + B4LN = SIO_BAR_LEN }
// UART0 - If (LNotEqual (\S5B1, Zero)) { + If (\S5B1 != 0) { CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) + B5AD = \S5B1 + B5LN = SIO_BAR_LEN }
// UART1 - If (LNotEqual (\S6B1, Zero)) { + If (\S6B1 != 0) { CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) + B6AD = \S6B1 + B6LN = SIO_BAR_LEN }
// SDIO - If (LNotEqual (\S7B1, Zero)) { + If (\S7B1 != 0) { CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) + B7AD = \S7B1 + B7LN = SIO_BAR_LEN }
Return (RBUF) @@ -158,11 +158,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S0B0, Zero)) { + If (\S0B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B0 + B0LN = SIO_BAR_LEN }
Return (RBUF) @@ -170,7 +170,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S0EN, 0)) { + If (\S0EN == 0) { Return (0x0) } Else { Return (0xF) @@ -214,15 +214,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S1B0, Zero)) { + If (\S1B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S1B0 + B0LN = SIO_BAR_LEN }
// Check if Serial IO DMA Controller is enabled - If (LNotEqual (_SB.PCI0.SDMA._STA, Zero)) { + If (_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -231,7 +231,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (0x0) } Else { Return (0xF) @@ -285,15 +285,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S2B0, Zero)) { + If (\S2B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S2B0 + B0LN = SIO_BAR_LEN }
// Check if Serial IO DMA Controller is enabled - If (LNotEqual (_SB.PCI0.SDMA._STA, Zero)) { + If (_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -302,7 +302,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S2EN, 0)) { + If (\S2EN == 0) { Return (0x0) } Else { Return (0xF) @@ -346,11 +346,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S3B0, Zero)) { + If (\S3B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S3B0 + B0LN = SIO_BAR_LEN }
Return (RBUF) @@ -358,7 +358,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S3EN, 0)) { + If (\S3EN == 0) { Return (0x0) } Else { Return (0xF) @@ -409,15 +409,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + If (\S4B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S4B0 + B0LN = SIO_BAR_LEN }
// Check if Serial IO DMA Controller is enabled - If (LNotEqual (_SB.PCI0.SDMA._STA, Zero)) { + If (_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -426,7 +426,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S4EN, 0)) { + If (\S4EN == 0) { Return (0x0) } Else { Return (0xF) @@ -477,15 +477,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { + If (\S5B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S5B0 + B0LN = SIO_BAR_LEN }
// Check if Serial IO DMA Controller is enabled - If (LNotEqual (_SB.PCI0.SDMA._STA, Zero)) { + If (_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -494,7 +494,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S5EN, 0)) { + If (\S5EN == 0) { Return (0x0) } Else { Return (0xF) @@ -538,11 +538,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S6B0, Zero)) { + If (\S6B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S6B0 + B0LN = SIO_BAR_LEN }
Return (RBUF) @@ -550,7 +550,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (0x0) } Else { Return (0xF) @@ -595,11 +595,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (\S7B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S7B0 + B0LN = SIO_BAR_LEN }
Return (RBUF) @@ -607,7 +607,7 @@
Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (\S7EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index 22e3cbc..6cc91a9 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -45,8 +45,7 @@ // Clear status bits Method (LPCL, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, (^XMEM << 16), 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] @@ -60,32 +59,31 @@ }
// Port Enabled/Disabled (Bit 1) - Name (PEDB, ShiftLeft (1, 1)) + Name (PEDB, (1 << 1))
// Change Status (Bits 23:17) - Name (CHST, ShiftLeft (0x7f, 17)) + Name (CHST, (0x7f << 17))
// Port 0 - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) + Local0 = PSC0 & ~PEDB + PSC0 = Local0 | CHST
// Port 1 - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) + Local0 = PSC1 & ~PEDB + PSC1 = Local0 | CHST
// Port 2 - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + Local0 = PSC2 & ~PEDB + PSC2 = Local0 | CHST
// Port 3 - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + Local0 = PSC3 & ~PEDB + PSC3 = Local0 | CHST }
Method (LPS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, (^XMEM << 16), 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3 @@ -131,16 +129,14 @@ }
// Wait for all powered ports to finish polling - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) + Local0 = 10 + While (((PPR1 == 1) && (PLS1 == PLSP)) || ((PPR2 == 1) && (PLS2 == PLSP)) || + ((PPR3 == 1) && (PLS3 == PLSP)) || ((PPR4 == 1) && (PLS4 == PLSP))) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) }
@@ -151,43 +147,37 @@ // 3) Write 1 to port status to clear
// Local# indicate if port is reset - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + Local1 = 0 + Local2 = 0 + Local3 = 0 + Local4 = 0
- If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset - Store (1, Local1) + If ((PLS1 == PLSD) && (CSC1 == 0) && (PPR1 == 1)) { + WPR1 = 1 // Issue warm reset + Local1 = 1 } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset - Store (1, Local2) + If ((PLS2 == PLSD) && (CSC2 == 0) && (PPR2 == 1)) { + WPR2 = 1 // Issue warm reset + Local2 = 1 } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset - Store (1, Local3) + If ((PLS3 == PLSD) && (CSC3 == 0) && (PPR3 == 1)) { + WPR3 = 1 // Issue warm reset + Local3 = 1 } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset - Store (1, Local4) + If ((PLS4 == PLSD) && (CSC4 == 0) && (PPR4 == 1)) { + WPR4 = 1 // Issue warm reset + Local4 = 1 }
// Poll for warm reset complete on all ports that were reset - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) + Local0 = 10 + While (((((Local1 == 1) && (WRC1 == 0)) || ((Local2 == 1) && (WRC2 == 0))) || + (((Local3 == 1) && (WRC3 == 0)) || ((Local4 == 1) && (WRC4 == 0))))) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) }
@@ -202,15 +192,14 @@
Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If ((^XMEM == 0xFFFF) || (^XMEM == 0x0000)) { Return () }
- OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -227,34 +216,34 @@ }
// If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 }
- if (LNot (\ISWP())) { + if (!\ISWP()) { // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) + ^MB13 = 0 + ^MB14 = 0
// Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) + CLK0 = 0 + CLK1 = 0
// Set MMIO 0x8154[31] - Store (1, CLK2) + CLK2 = 1
// Handle per-port reset if needed LPS0 ()
// Set MMIO 0x80e0[15] - Store (1, AX15) + AX15 = 1
// Clear PCI CFG offset 0x40[11] - Store (0, ^SWAI) + ^SWAI = 0
// Clear PCI CFG offset 0x44[13:12] - Store (0, ^SAIP) + ^SAIP = 0 }
Return () @@ -262,15 +251,14 @@
Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If ((^XMEM == 0xFFFF) || (^XMEM == 0x0000)) { Return () }
- OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -286,39 +274,39 @@ CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable }
- Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME + ^PMES = 1 // Clear PME Status + ^PMEE= 1 // Enable PME
// If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 }
- if (LNot (\ISWP())) { + if (!\ISWP()) { // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) + ^MB13 = 1 + ^MB14 = 1
// Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) + CLK0 = 1 + CLK1 = 1
// Clear MMIO 0x8154[31] - Store (0, CLK2) + CLK2 = 0
// Clear MMIO 0x80e0[15] - Store (0, AX15) + AX15 = 0
// Set PCI CFG offset 0x40[11] - Store (1, ^SWAI) + ^SWAI = 1
// Set PCI CFG offset 0x44[13:12] - Store (1, ^SAIP) + ^SAIP = 1 }
// Put device in D3 - Store (3, ^D0D3) + ^D0D3 = 3
Return () } @@ -348,12 +336,12 @@ })
// REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + CreateField (DerefOf (PCKG [0]), Zero, 0x07, REV) + REV = 0x02
// VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, One, VISI) + VISI = Arg0 Return (PCKG) }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46238
to look at the new patch set (#2).
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/xhci.asl 9 files changed, 264 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46238
to look at the new patch set (#3).
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/xhci.asl 9 files changed, 264 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/3
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46238
to look at the new patch set (#4).
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/xhci.asl 9 files changed, 264 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46238
to look at the new patch set (#5).
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/xhci.asl 9 files changed, 266 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/5
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46238 )
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
Patch Set 5: Code-Review+2
Hello build bot (Jenkins), Stefan Reinauer, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46238
to look at the new patch set (#6).
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/broadwell/pch/acpi/gpio.asl 1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46238/6
Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46238 )
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
Patch Set 7: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46238 )
Change subject: soc/intel/broadwell: Convert to ASL 2.0 syntax ......................................................................
soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/46238 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/acpi/gpio.asl 1 file changed, 8 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl index 6b20f27..bd9f581 100644 --- a/src/soc/intel/broadwell/pch/acpi/gpio.asl +++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl @@ -58,17 +58,18 @@ Method (GWAK, 1, Serialized) { // Local0 = GPIO Base Address - Store (GPBS & ~1, Local0) + Local0 = GPBS & ~1
// Local1 = BANK, Local2 = OFFSET - Divide (Arg0, 32, Local2, Local1) + Local2 = Arg0 % 32 + Local1 = Arg0 / 32
// // Set OWNER to ACPI //
// Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Local0 + Local1 * 4, Local3) + Local3 = Local0 + (Local1 * 4)
// GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -77,14 +78,14 @@ }
// GPIO_OWN[GPIO] = 0 (ACPI) - Store (GOWN & ~(1 << Local2), GOWN) + GOWN = GOWN & ~(1 << Local2)
// // Set ROUTE to SCI //
// Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Local0 + 0x30 + Local1 * 4, Local3) + Local3 = Local0 + 0x30 + (Local1 * 4)
// GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -93,14 +94,14 @@ }
// GPIO_ROUTE[GPIO] = 0 (SCI) - Store (GROU & ~(1 << Local2), GROU) + GROU = GROU & ~(1 << Local2)
// // Set GPnCONFIG to GPIO|INPUT|INVERT //
// Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Local0 + 0x100 + Arg0 * 8, Local3) + Local3 = Local0 + 0x100 + (Arg0 * 8)
// GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8)