Change in coreboot[master]: nb/intel/x4x: Correct and use macros for CLKCFG

[Angel Pons (Code Review)]

Attention is currently required from: Damien Zammit, Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51877 )

Change subject: nb/intel/x4x: Correct and use macros for CLKCFG
......................................................................

nb/intel/x4x: Correct and use macros for CLKCFG

The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and
use the CLKCFG macros instead of magic values.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/x4x.h
4 files changed, 7 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/51877/1

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index f942d59..e6083d9 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -62,7 +62,7 @@
    EPBAR8(EPVC0RCTL) = 1;
    EPBAR8(EPPVCCAP1) = 1;

-	switch (MCHBAR32(0xc00) & 0x7) {
+	switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
    case 0x0:
    	/* FSB 1066 */
    	EPBAR32(EPVC1ITC) = 0x0001a6db;
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 692c4e9..78946c3 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -412,7 +412,7 @@

static void find_fsb_speed(struct sysinfo *s)
 {
-	switch (MCHBAR32(0xc00) & 0x7) {
+	switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
    case 0x0:
    	s->max_fsb = FSB_CLOCK_1066MHz;
    	break;
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 84dbff5..6863ef8 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1952,11 +1952,12 @@
    		MCHBAR8_OR(0x1a8, 0x4);

/* Set frequency */
-		MCHBAR32_AND_OR(0xc00, ~0x70,
-			(s->selected_timings.mem_clk << 4) | (1 << 10));
+		MCHBAR32_AND_OR(CLKCFG_MCHBAR, ~CLKCFG_MEMCLK_MASK,
+			(s->selected_timings.mem_clk << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE);

/* Overwrite value if chipset rejects it */
-		s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4;
+		s->selected_timings.mem_clk =
+			(MCHBAR8(CLKCFG_MCHBAR) & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT;
    	if (s->selected_timings.mem_clk > (s->max_fsb + 3))
    		die("Error: DDR is faster than FSB, halt\n");
    }
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 0c0e605..991d175 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -74,7 +74,7 @@
 #define CLKCFG_FSBCLK_MASK	(7 << CLKCFG_FSBCLK_SHIFT)
 #define CLKCFG_MEMCLK_SHIFT	4
 #define CLKCFG_MEMCLK_MASK	(7 << CLKCFG_MEMCLK_SHIFT)
-#define CLKCFG_UPDATE		(1 << 12)
+#define CLKCFG_UPDATE		(1 << 10)

#define SSKPD_MCHBAR		0x0c20 /* 64 bit */