Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Paul Menzel, Tim Wawrzynczak, Ravindra, Sridhar Siricilla, Michael Niewöhner, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )

Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> Having read this code I'm very much unconvinced of the code to count big/small core into a bitmask a […]

Looking at code and referring to the sample implementation, I think below are only changes that we need to support
hybrid/heterogeneous cause for ADL.

#define SCALING_FACTOR_CORE_SMALL 100
#define SCALING_FACTOR_CORE_BIG 127
// note, this should come from SoC only not from common code, as there might be different value for MTL/LNL etc.

// max_non_turbo_ratio = https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...
#define GET_OVERRIDE_NOMINAL_FREQ(max_non_turbo_ratio, core_type) ((max_non_turbo_ratio * SCALING_FACTOR_CORE_##core_type)/100)

get_core_type => preferably return an enum between BIG and SMALL
 - Based on SOC Kconfig, for ADL-N, you can safely return ADL-N as SMALL
 - For others, cpuid leaf fn can be implemented in IA-common core to return the core type

Sample Override Function:
1. We can use ADL SoC Kconfig for P/M/N to safely say the platform supports Nominal Freq override
2. Implement function/macro to calculate the Nominal overridden value for Big and Small core
   - sample above GET_OVERRIDE_NOMINAL_FREQ macro
3. Check the core type, sample function above (get_core_type)
4. Based on the core type from #3 above.
   - Override _CPC table nominal perf element using #2 macro implementation.

Scope(_SB.PR00)
{
// Perform Nominal Freq override if support by platform
// (Supported platform are ADL-P/M and N)
// to _CPC fields for supporting heterogeneous core
Return (CPC3)
}

Scope(_SB.PR01)
{

}

...

Scope(_SB.PR0n)
{

}

Good part of coreboot implementation is that
1. We are using 'C' code to create a runtime SSDT hence, we can use
those checks as mentioned in #1 above easily.
2. Don't need any GNVS.
3. Don't need to create any new cpu_index() function that returns sorted cpu index.
4. You can run this entire implementation using coreboot MP code so that #3 can get satisfied.