Change in coreboot[master]: cpu/amd/quadcore: Correct checkpatch errors

[Logan Carlson (Code Review)]

Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19990 )

Change subject: cpu/amd/quadcore: Correct checkpatch errors
......................................................................

cpu/amd/quadcore: Correct checkpatch errors

Correct issues with whitespace found in cpu/amd/quadcore.

Change-Id: Idc48d1177db474649cddd8a2f496e330eaabb113
Signed-off-by: Logan Carlson 
---
M src/cpu/amd/quadcore/amd_sibling.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/amd/quadcore/quadcore_id.c
3 files changed, 12 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19990/1

diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index c4eb50c..526dc0d 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -41,7 +41,7 @@
    u32 siblings=0;

//get max siblings from all the nodes
-	for (nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid = 0; nodeid < nodes; nodeid++) {
    	int j;
    	dev = get_node_pci(nodeid, 3);
    	j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
@@ -60,7 +60,7 @@
    u32 nodeid;

//enable APIC_EXIT_ID all the nodes
-	for (nodeid=0; nodeid<nodes; nodeid++){
+	for (nodeid = 0; nodeid < nodes; nodeid++) {
    	u32 val;
    	dev = get_node_pci(nodeid, 0);
    	val = pci_read_config32(dev, 0x68);
@@ -82,9 +82,11 @@

siblings = get_max_siblings(sysconf.nodes);

-	if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0
+	if (sysconf.bsp_apicid > 0) {
+		// IOAPIC could start from 0
    	return 0;
-	} else if (sysconf.enabled_apic_ext_id)	{ // enabled ext id but bsp = 0
+	} else if (sysconf.enabled_apic_ext_id)	{
+		// enabled ext id but bsp = 0
    	return 1;
    }

@@ -93,7 +95,7 @@

//Construct apicid_base

-	if ((!disable_siblings) && (siblings>0) ) {
+	if ((!disable_siblings) && (siblings > 0)) {
    	/* for 8 way dual core, we will used up apicid 16:16, actually
    	   16 is not allowed by current kernel and the kernel will try
    	   to get one that is small than 16 to make IOAPIC work. I don't
@@ -108,7 +110,7 @@
    	apicid_base = sysconf.nodes;
    }

-	if ((apicid_base+ioapic_num-1)>0xf) {
+	if ((apicid_base+ioapic_num-1) > 0xf) {
    	// We need to enable APIC EXT ID
    	printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
    	enable_apic_ext_id(sysconf.nodes);
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 2f0822e..d4f0dd7 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -34,9 +34,9 @@
    	dword >>= 12;
    	/* Bit 15 is CmpCap[2] since Revision D. */
    	if ((cpuid_ecx(0x80000008) & 0xff) > 3)
-	    	dword = ((dword & 8) >> 1) | (dword & 3);
+			dword = ((dword & 8) >> 1) | (dword & 3);
    	else
-	    	dword &= 3;
+			dword &= 3;
    }
    return dword;
 }
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index cd83906..f2a9e1a 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -26,7 +26,7 @@
 {
    msr_t msr;
    msr = rdmsr(NB_CFG_MSR);
-	return ( ( msr.hi >> (54-32)) & 1);
+	return ((msr.hi >> (54-32)) & 1);
 }

u32 get_initial_apicid(void)
@@ -75,7 +75,7 @@
     * The apicid format varies based on processor revision
     */
    apicid = (cpuid_ebx(1) >> 24) & 0xff;
-	if ( nb_cfg_54) {
+	if (nb_cfg_54) {
    	if (fam15h && dual_node) {
    		id.coreid = apicid & 0x1f;
    		id.nodeid = (apicid & 0x60) >> 5;