New patch to review for coreboot: rockchip: rk3288: correct ddr 300MHz clock setting

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10772

-gerrit

commit 28e0f3caae412039ba0a33d2c295886bd65ea9c5
Author: huang lin 
Date:   Tue Jun 30 10:01:14 2015 +0800

rockchip: rk3288: correct ddr 300MHz clock setting

CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
    setting can't meet this request, so modify it

BRANCH=None
    BUG=None
    TEST=Set ddr frequency to 300MHz and boot from mickey

Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5
    Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f
    Original-Signed-off-by: huang lin 
    Original-Reviewed-on: https://chromium-review.googlesource.com/282445
    Original-Reviewed-by: David Hendricks 
    Original-Reviewed-by: Julius Werner 
---
 src/soc/rockchip/rk3288/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index b823e01..878c194 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -360,7 +360,7 @@ void rkclk_configure_ddr(unsigned int hz)

switch (hz) {
    case 300*MHz:
-		dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1};
+		dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2};
    	break;
    case 533*MHz:	/* actually 533.3P MHz */
    	dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};