Attention is currently required from: Martin Roth, Furquan Shaikh, Aaron Durbin, Karthik Ramasubramanian. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 )
Change subject: soc/intel: Remove SMM HECI disable related options ......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/cannonlake/smihandler.c:
https://review.coreboot.org/c/coreboot/+/52147/comment/0dde57cc_6075abf5 PS2, Line 22: const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); : if (!is_dev_enabled(dev))
The concerned PCI device (device pci 16.0) is also enabled/disabled in devicetree. […]
Ack
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/52147/comment/c5f3f098_afd7a55b PS3, Line 5: y
We may have to change it to $(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE)
There's still the port ID issue on some of the SoCs. Some of them don't define `PID_CSME0`. I assume the component is there, but it'll take same digging to determine what it ought to be.
I think I'm going to restrict the changes to just dedede for now and then file a bug for the further cleanup.