Change in coreboot[master]: soc/amd/stoneyridge: Generate SPCR table

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25345

Change subject: soc/amd/stoneyridge: Generate SPCR table
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soc/amd/stoneyridge: Generate SPCR table

Add the Serial Port Console Redirection Table to Stoney's ACPI tables.
Stoney customizes the OEM and OEM_TABLE IDs to notify the linux kernel
of of the custom input clock.

BUG=b:74392237
TEST=Build Grunt, verify SPCR table

Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b
Signed-off-by: Martin Roth 
---
M src/soc/amd/stoneyridge/acpi.c
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25345/1

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 02ee6fa..4fa06e9 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -262,6 +262,21 @@
    	unsigned long current,
    	struct acpi_rsdp *rsdp)
 {
+	acpi_spcr_t * spcr = (void *)current;
+	current = acpi_create_spcr(current);
+	if (current != (unsigned long)spcr) {
+		/*
+		 * Update SPCR IDs for Stoney so Linux can configure the input
+		 * clock in order to compute the baud rate divisor registers.
+		 */
+		memcpy(spcr->header.oem_id, "AMDCZ ", 6);
+		memcpy(spcr->header.oem_table_id, "AMDCZ   ", 8);
+		spcr->header.checksum = 0; /* clear before re-chesksumming */
+		spcr->header.checksum = acpi_checksum((void *)spcr,
+				spcr->header.length);
+		acpi_add_table(rsdp, (void *)spcr);
+	}
+
    return acpi_write_hpet(device, current, rsdp);
 }