[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Bill XIE (Code Review)]

Attention is currently required from: Keith Hui.

Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 2:

(2 comments)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/8c351c64_bf676bde?usp... :
PS1, Line 67: gpio5 |= 0x20;
> I think I have all GPIO signals figured out, and wrote what I found into early_init.c. […]

PCHSTRP9  : 0x30004d80, I also have another three descriptors with PCHSTRP9 0x30004d81, 0x30004d82, 0x30004d83. My board's PCB revision is 1.02.

pcie_rp4 remains wired to ASM1061 when a card is present on PCIEX1_2, inteltool says:
gpiobase+0x000c: 0xe8ab7ffe (GP_LVL)
and superiotool said:
LDN 0x09
idx 30 ... f4 f5 ...
val ff ... 8f c8 ...
def 00 ... ff 00 ...
If no card is present on PCIEX1_2, GP_LVL is 0xe8bb7ffe and LDN 0x09 is
idx 30 ... f4 f5 ...
val ff ... 8f c8 ...
def 00 ... ff 00 ...

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/c7f50048_5a08efd1?usp... :
PS2, Line 77: {7, 34, 20, -1}
This order should be reversed to {20, 34, 7, -1}, as get_gpios() works in little-endian way.

When fixed, pcie_rp4 is wired to ASM1061 without card on PCIEX1_2:
LDN 0x09
idx 30 ... f4 f5 ...
val ff ... 8f c8 ...
def 00 ... ff 00 ...
but to nothing with card on PCIEX1_2:
LDN 0x09
idx 30 ... f4 f5 ...
val ff ... 8f a8 ...
def 00 ... ff 00 ...