Change in coreboot[master]: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.

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Meera Ravindranath (Code Review)

3 Feb 2020 3 Feb '20

5:10 p.m.

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports. ......................................................................

src/soc/tigerlake: Define and use a Kconfig for no of USB ports.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 3 files changed, 14 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/1

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..f50e40e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -156,6 +156,16 @@ default 3 if SOC_INTEL_JASPERLAKE default 4 if SOC_INTEL_TIGERLAKE

+config SOC_INTEL_USB2_DEV_MAX + int + default 8 if SOC_INTEL_JASPERLAKE + default 10 if SOC_INTEL_TIGERLAKE + +config SOC_INTEL_USB3_DEV_MAX + int + default 6 if SOC_INTEL_JASPERLAKE + default 4 if SOC_INTEL_TIGERLAKE + config SOC_INTEL_I2C_DEV_MAX int default 6 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8046b2e..d5d623b 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -106,7 +106,7 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

/* USB configuration */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) {

params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -116,7 +116,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; }

- for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) {

params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..f027ee0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -89,7 +89,7 @@ params->IomTypeCPortPadCfg[i] = 0x09000000;

/* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; @@ -98,7 +98,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; }

- for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) {

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Aamir Bohra (Code Review)

4 Feb 4 Feb

2:45 a.m.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports. ......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG@7 PS1, Line 7: rc/soc/tigerlake: Define and use a Kconfig for no of USB ports. Can we add a small description.

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG@7 PS1, Line 7: . Define and use config for number of USB2/3 ports

https://review.coreboot.org/c/coreboot/+/38682/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/38682/1/src/soc/intel/tigerlake/Kco... PS1, Line 159: DEV port

Meera Ravindranath (Code Review)

3:54 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Hello Patrick Rudolph, Aamir Bohra, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#2).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports. ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Using a config for no of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/2

Meera Ravindranath (Code Review)

3:57 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Hello Patrick Rudolph, Aamir Bohra, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#3).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports. ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Using a config for no of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/3

Meera Ravindranath (Code Review)

4:01 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Hello Patrick Rudolph, Aamir Bohra, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#4).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports. ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Using a config for no of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/4

Aamir Bohra (Code Review)

8:03 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports. ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/4//COMMIT_MSG@7 PS4, Line 7: . not needed.

https://review.coreboot.org/c/coreboot/+/38682/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/4/src/soc/intel/tigerlake/fsp... PS4, Line 111: usb2_ports[i] the chip.h also needs to be updated to have array size defined as per config.

Meera Ravindranath (Code Review)

9:56 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Hello Patrick Rudolph, Sridhar Siricilla, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#5).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports

Using a config for no of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 4 files changed, 16 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/5

Meera Ravindranath (Code Review)

10:47 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 5:

(5 comments)

...

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG@7 PS1, Line 7: .

...

Define and use config for number of USB2/3 ports

Done

https://review.coreboot.org/c/coreboot/+/38682/1//COMMIT_MSG@7 PS1, Line 7: rc/soc/tigerlake: Define and use a Kconfig for no of USB ports.

...

Can we add a small description.

Done

https://review.coreboot.org/c/coreboot/+/38682/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/4//COMMIT_MSG@7 PS4, Line 7: .

...

not needed.

Done

https://review.coreboot.org/c/coreboot/+/38682/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/38682/1/src/soc/intel/tigerlake/Kco... PS1, Line 159: DEV

...

port

Done

https://review.coreboot.org/c/coreboot/+/38682/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/4/src/soc/intel/tigerlake/fsp... PS4, Line 111: usb2_ports[i]

...

the chip.h also needs to be updated to have array size defined as per config.

Done

Aamir Bohra (Code Review)

5 Feb 5 Feb

9:07 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 5:

the jasperlake_rvp devicetree also needs to be aligned now as per updated port count.

Meera Ravindranath (Code Review)

6 Feb 6 Feb

4:43 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#6).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports

Using a config for no of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 5 files changed, 16 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/6

Meera Ravindranath (Code Review)

4:44 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 6:

...

Patch Set 5:

the jasperlake_rvp devicetree also needs to be aligned now as per updated port count.

Done

Aamir Bohra (Code Review)

5:49 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 6: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Balaji Manigandan balaji.manigandan@intel.com Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 06 Feb 2020 17:49:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Aamir Bohra (Code Review)

8 Feb 8 Feb

3:38 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Aamir Bohra has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Removed Code-Review+1 by Aamir Bohra aamir.bohra@intel.com

Aamir Bohra (Code Review)

10 Feb 10 Feb

11:21 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 6: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG@9 PS6, Line 9: no number of

-- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Balaji Manigandan balaji.manigandan@intel.com Gerrit-Reviewer: Justin TerAvest teravest@chromium.org Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Mon, 10 Feb 2020 11:21:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Rizwan Qureshi (Code Review)

12 Feb 12 Feb

10:57 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG@10 PS6, Line 10: and jsl in fsp params. This patch is also fixing the devictree.cb for jasperlake_rvp, care to mention that?

-- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Balaji Manigandan balaji.manigandan@intel.com Gerrit-Reviewer: Justin TerAvest teravest@chromium.org Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 12 Feb 2020 10:57:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Meera Ravindranath (Code Review)

11:40 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Aamir Bohra, Wonkyu Kim, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#7).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports

Using a config for number of USB2/3 ports to be able to handle both tgl and jsl in fsp params.

BUG=None BRANCH=None TEST=Compilation for jasper lake board is working

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Balaji Manigandan balaji.manigandan@intel.com Gerrit-Reviewer: Justin TerAvest teravest@chromium.org Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Karthik Ramasubramanian (Code Review)

13 Feb 13 Feb

6:32 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 7:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG@9 PS6, Line 9: no

...

number of

Done

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG@10 PS6, Line 10: and jsl in fsp params.

...

This patch is also fixing the devictree. […]

Still the commit message not fixed. LGTM otherwise.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Aamir Bohra aamir.bohra@intel.com Gerrit-Reviewer: Balaji Manigandan balaji.manigandan@intel.com Gerrit-Reviewer: Justin TerAvest teravest@chromium.org Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com Gerrit-Reviewer: Meera Ravindranath meera.ravindranath@intel.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 13 Feb 2020 18:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra aamir.bohra@intel.com Comment-In-Reply-To: Rizwan Qureshi rizwan.qureshi@intel.com Gerrit-MessageType: comment

Meera Ravindranath (Code Review)

14 Feb 14 Feb

6:25 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Hello Patrick Rudolph, Karthik Ramasubramanian, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Aamir Bohra, Wonkyu Kim, Justin TerAvest, Rizwan Qureshi, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#8).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports

Using a config for number of USB2/3 ports to be able to handle both tgl and jsl in fsp params. Also, removing the unused USB2 ports from the devicetree.

BUG=None BRANCH=None TEST=Compilation for JasperLake board is working

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/8

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Meera Ravindranath (Code Review)

6:27 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/6//COMMIT_MSG@10 PS6, Line 10: and jsl in fsp params.

...

Still the commit message not fixed. LGTM otherwise.

Done

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Karthik Ramasubramanian (Code Review)

6:38 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8: Code-Review+2

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Paul Menzel (Code Review)

1:14 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@9 PS8, Line 9: Using Use

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 PS8, Line 10: and jsl in fsp params. The hardware should be described in the device tree. Isn’t there another way?

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@11 PS8, Line 11: Also, removing the unused USB2 ports from the devicetree. Please add a blank line above.

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@15 PS8, Line 15: JasperLake Jasper Lake

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Nico Huber (Code Review)

1:47 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 PS8, Line 10: and jsl in fsp params. Won't the TGL FSP also support PCH-H? It seems the new numbers are for PCH-LP only.

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... PS8, Line 108: for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) { How about `ARRAY_SIZE(params->PortUsb20Enable)` instead? It's always better to use the target size to avoid writing to undefined memory.

We should, in any case, assert that we don't make wrong assumptions about the UPDs. e.g. with the size as above:

_Static_assert(ARRAY_SIZE(params->PortUsb20Enable) <= ARRAY_SIZE(config->usb2_ports));

Then we were also sure that we don't read from undefined locations. This way we wouldn't need more Kconfigs and would be safer.

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Nico Huber (Code Review)

1:47 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8: Code-Review-1

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Meera Ravindranath (Code Review)

17 Feb 17 Feb

2:01 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 PS8, Line 10: and jsl in fsp params.

...

Won't the TGL FSP also support PCH-H? It seems the new numbers are […]

We do not have any mainboards added for PCH-H as of now. So we would like to support that on a need basis.

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... PS8, Line 108: for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) {

...

How about `ARRAY_SIZE(params->PortUsb20Enable)` instead? It's always better […]

Hello Nico. This is a valid point. But ARRAY_SIZE(params->PortUsb20Enable) would be 16 whereas JSL and TGL supports 8 and 10 USB2 ports respectively. With 16 as array size we would be running the for loop more than required. So the Kconfig way of defining the array size was to eliminate this and run the loop for required numbers for both JSL and TGL based on the no of usb ports they support. Please let me know your thoughts on this.

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Nico Huber (Code Review)

2:10 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 PS8, Line 10: and jsl in fsp params.

...

We do not have any mainboards added for PCH-H as of now. […]

Ack.

Though, it shows that your approach creates more work in case somebody wants to add those in the future.

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... PS8, Line 108: for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) {

...

Hello Nico. […]

Writing more error-prone code (people have to maintain the correct numbers in Kconfig, make sure they agree with external header files and that an external program (FSP) does it's job well even if not all of its inputs are set to a defined state), is not worth saving 6 loop iterations, imho.

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Duncan Laurie (Code Review)

8:39 p.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8:

Please also update the ACPI names at https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src...

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Karthik Ramasubramanian (Code Review)

19 Feb 19 Feb

4:30 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Patch Set 8: -Code-Review

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Meera Ravindranath (Code Review)

3 Dec 3 Dec

10:54 a.m.

New subject: Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

Meera Ravindranath has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................

Abandoned

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participants (7)

Aamir Bohra (Code Review)
Duncan Laurie (Code Review)
Karthik Ramasubramanian (Code Review)
Meera Ravindranath (Code Review)
Nico Huber (Code Review)
Paul Menzel (Code Review)
Rizwan Qureshi (Code Review)