Change in coreboot[master]: mb/google/poppy/variants/nocturne: Update DPTF settings

[Puthikorn Voravootivat (Code Review)]

Puthikorn Voravootivat has uploaded this change for review. ( https://review.coreboot.org/28738

Change subject: mb/google/poppy/variants/nocturne: Update DPTF settings
......................................................................

mb/google/poppy/variants/nocturne: Update DPTF settings

The previous does not work well enough when testing with
high ambient temperature. Update DPTF settings to make
it work better.

BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.

Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a
Signed-off-by: Puthikorn Voravootivat 
---
M 3rdparty/blobs
M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
2 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/28738/1

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 372012e..c285102 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 372012e8e1d0d01f3e77ff73b118665b41ff68b6
+Subproject commit c2851026e72dcb7b8c1d19e750c0416a6abf41ce
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
index f9773b8..40c7f63 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
@@ -30,7 +30,7 @@
 #define DPTF_TSR2_SENSOR_ID		3
 #define DPTF_TSR2_SENSOR_NAME		"DRAM"
 #define DPTF_TSR2_PASSIVE		45
-#define DPTF_TSR2_CRITICAL		48
+#define DPTF_TSR2_CRITICAL		55

#define DPTF_TSR3_SENSOR_ID		4
 #define DPTF_TSR3_SENSOR_NAME		"eMMC"
@@ -56,7 +56,7 @@
    Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },

/* CPU Throttle Effect on DRAM (TSR2) */
-	Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 },

/* CPU Throttle Effect on eMMC (TSR3) */
    Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
@@ -66,7 +66,7 @@
    Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },

/* Charger Throttle Effect on DRAM (TSR2) */
-	Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 },
 #endif
 })