[M] Change in coreboot[master]: soc/intel/cmn/tom: Cache TOM region early

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli, Jamie Ryu, Paul Menzel, Kapil Porwal.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73272 )

Change subject: soc/intel/cmn/tom: Cache TOM region early
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/73272/comment/824decc2_9db858b0 
PS1, Line 12:
> > Why is determining TOM take 50 ms? Please elaborate in the commit message.
>
> please read the line between 13-19, that explains why we are seeing 50ms savings (FSP-M and late romstage uses this
> uncached TOM range for various purposes). Sorry! I don't know how to make more elaborative commit msg.

I have added some more explicit statements, hope it makes things easy to understand.