Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some pervious work for Skylake (https://review.coreboot.org/c/coreboot/+/23462) to common DPTF code so that we can support mode-aware DPTF for all Intel platforms.
BUG=b:138702459
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/1
diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index c8aa037..ca128c9 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -59,7 +59,50 @@ #endif }
+/* Thermal Trip Points Change Event Handler */ +Method (TPET) +{ #ifdef DPTF_TSR0_SENSOR_ID + Notify (^TSR0, 0x81) +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Notify (^TSR1, 0x81) +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Notify (^TSR2, 0x81) +#endif +#ifdef DPTF_TSR3_SENSOR_ID + Notify (^TSR3, 0x81) +#endif +} + +/* + * Method to return trip temperature value depending upon the device mode. + * Arg0 --> Value to return when device is in tablet mode + * Arg1 --> Value to return when device is not in tablet mode. + */ +Method (DTRP, 2, Serialized) +{ +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + If (LEqual (_SB.PCI0.LPCB.EC0.RCDP, One)) { + Return (CTOK (Arg0)) + } Else { +#endif + Return (CTOK (Arg1)) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + } +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID + +#ifndef DPTF_TSR0_TABLET_PASSIVE +#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE +#endif +#ifndef DPTF_TSR0_TABLET_CRITICAL +#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL +#endif + Device (TSR0) { Name (_HID, EISAID ("INT3403")) @@ -85,12 +128,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR0_PASSIVE)) + Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR0_CRITICAL)) + Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL)) }
Name (PATC, 2) @@ -116,6 +159,14 @@ #endif
#ifdef DPTF_TSR1_SENSOR_ID + +#ifndef DPTF_TSR1_TABLET_PASSIVE +#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE +#endif +#ifndef DPTF_TSR1_TABLET_CRITICAL +#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL +#endif + Device (TSR1) { Name (_HID, EISAID ("INT3403")) @@ -141,12 +192,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR1_PASSIVE)) + Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR1_CRITICAL)) + Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL)) }
Name (PATC, 2) @@ -172,6 +223,14 @@ #endif
#ifdef DPTF_TSR2_SENSOR_ID + +#ifndef DPTF_TSR2_TABLET_PASSIVE +#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE +#endif +#ifndef DPTF_TSR2_TABLET_CRITICAL +#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL +#endif + Device (TSR2) { Name (_HID, EISAID ("INT3403")) @@ -197,12 +256,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR2_PASSIVE)) + Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR2_CRITICAL)) + Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL)) }
Name (PATC, 2) @@ -228,6 +287,14 @@ #endif
#ifdef DPTF_TSR3_SENSOR_ID + +#ifndef DPTF_TSR3_TABLET_PASSIVE +#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE +#endif +#ifndef DPTF_TSR3_TABLET_CRITICAL +#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL +#endif + Device (TSR3) { Name (_HID, EISAID ("INT3403")) @@ -253,12 +320,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR3_PASSIVE)) + Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR3_CRITICAL)) + Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL)) }
Name (PATC, 2)
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG@14 PS1, Line 14: Add TEST details here for reference. Also, add BRANCH=None.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG@10 PS1, Line 10: (https://review.coreboot.org/c/coreboot/+/23462) to common DPTF code Please use the commit message hash and summary (and Change-Id).
Hello Patrick Rudolph, Sumeet R Pawnikar, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34785
to look at the new patch set (#2).
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some pervious work for Skylake (cb58683ef581708fd256b875e05ed7263f867ab1) to common DPTF code so that we can support mode-aware DPTF for all Intel platforms.
BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE in hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/existing tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell)
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/2
Hello Patrick Rudolph, Sumeet R Pawnikar, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34785
to look at the new patch set (#3).
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some pervious work for Skylake:
cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF
...to common DPTF code so that we can support mode-aware DPTF for other Intel platforms.
BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE in hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/existing tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell)
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/3
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG@10 PS1, Line 10: (https://review.coreboot.org/c/coreboot/+/23462) to common DPTF code
Please use the commit message hash and summary (and Change-Id).
Done
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG@14 PS1, Line 14:
Add TEST details here for reference. […]
Done
Hello Patrick Rudolph, Sumeet R Pawnikar, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34785
to look at the new patch set (#4).
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some pervious work for Skylake:
cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF
...to common DPTF code so that we can support mode-aware DPTF for other Intel platforms.
BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE to hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/exiting tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell)
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34785/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/4//COMMIT_MSG@9 PS4, Line 9: pervious previous
Hello Patrick Rudolph, Paul Fagerburg, Sumeet R Pawnikar, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34785
to look at the new patch set (#5).
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some previous work for Skylake:
cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF
...to common DPTF code so that we can support mode-aware DPTF for other Intel platforms.
BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE to hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/exiting tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell)
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/5
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34785/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/4//COMMIT_MSG@9 PS4, Line 9: pervious
previous
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5: Code-Review+1
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5: Code-Review+1
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5:
Can we merge this patch?
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34785/1//COMMIT_MSG@14 PS1, Line 14:
Done
BRANCH=None is not necessary for coreboot.org changes.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
Patch Set 5:
We should move this to SSDT eventually. Lot of duplication can be avoided here.
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some previous work for Skylake:
cb58683ef5 soc/intel/skylake: Add support for mode-aware DPTF
...to common DPTF code so that we can support mode-aware DPTF for other Intel platforms.
BUG=b:138702459 BRANCH=none TEST=Manually test on hatch: (1)Add DPTF_TSR0_TABLET_PASSIVE and DPTF_TSR1_TABLET_PASSIVE to hatch baseboard dptf.asl (2)Flash custom EC FW code which updates DPTF profile number when entering/exiting tablet mode (3)On DUT, see /sys/class/thermal/thermal_zone2/trip_point_{1,2}_temp updated when device mode is switched (tablet/clamshell)
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34785 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index c8aa037..ca128c9 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -59,7 +59,50 @@ #endif }
+/* Thermal Trip Points Change Event Handler */ +Method (TPET) +{ #ifdef DPTF_TSR0_SENSOR_ID + Notify (^TSR0, 0x81) +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Notify (^TSR1, 0x81) +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Notify (^TSR2, 0x81) +#endif +#ifdef DPTF_TSR3_SENSOR_ID + Notify (^TSR3, 0x81) +#endif +} + +/* + * Method to return trip temperature value depending upon the device mode. + * Arg0 --> Value to return when device is in tablet mode + * Arg1 --> Value to return when device is not in tablet mode. + */ +Method (DTRP, 2, Serialized) +{ +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + If (LEqual (_SB.PCI0.LPCB.EC0.RCDP, One)) { + Return (CTOK (Arg0)) + } Else { +#endif + Return (CTOK (Arg1)) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + } +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID + +#ifndef DPTF_TSR0_TABLET_PASSIVE +#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE +#endif +#ifndef DPTF_TSR0_TABLET_CRITICAL +#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL +#endif + Device (TSR0) { Name (_HID, EISAID ("INT3403")) @@ -85,12 +128,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR0_PASSIVE)) + Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR0_CRITICAL)) + Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL)) }
Name (PATC, 2) @@ -116,6 +159,14 @@ #endif
#ifdef DPTF_TSR1_SENSOR_ID + +#ifndef DPTF_TSR1_TABLET_PASSIVE +#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE +#endif +#ifndef DPTF_TSR1_TABLET_CRITICAL +#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL +#endif + Device (TSR1) { Name (_HID, EISAID ("INT3403")) @@ -141,12 +192,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR1_PASSIVE)) + Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR1_CRITICAL)) + Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL)) }
Name (PATC, 2) @@ -172,6 +223,14 @@ #endif
#ifdef DPTF_TSR2_SENSOR_ID + +#ifndef DPTF_TSR2_TABLET_PASSIVE +#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE +#endif +#ifndef DPTF_TSR2_TABLET_CRITICAL +#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL +#endif + Device (TSR2) { Name (_HID, EISAID ("INT3403")) @@ -197,12 +256,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR2_PASSIVE)) + Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR2_CRITICAL)) + Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL)) }
Name (PATC, 2) @@ -228,6 +287,14 @@ #endif
#ifdef DPTF_TSR3_SENSOR_ID + +#ifndef DPTF_TSR3_TABLET_PASSIVE +#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE +#endif +#ifndef DPTF_TSR3_TABLET_CRITICAL +#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL +#endif + Device (TSR3) { Name (_HID, EISAID ("INT3403")) @@ -253,12 +320,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR3_PASSIVE)) + Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR3_CRITICAL)) + Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL)) }
Name (PATC, 2)
-
Furquan Shaikh (Code Review) -
Lance Zhao (Code Review)
-
Paul Fagerburg (Code Review)
-
Paul Menzel (Code Review)
-
Philip Chen (Code Review)
-
Sumeet R Pawnikar (Code Review)
-
Tim Wawrzynczak (Code Review)