Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34785 )
Change subject: soc/intel/common/dptf: Add support for mode-aware DPTF ......................................................................
soc/intel/common/dptf: Add support for mode-aware DPTF
This change ports some pervious work for Skylake (https://review.coreboot.org/c/coreboot/+/23462) to common DPTF code so that we can support mode-aware DPTF for all Intel platforms.
BUG=b:138702459
Signed-off-by: Philip Chen philipchen@google.com Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544 --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 75 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34785/1
diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index c8aa037..ca128c9 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -59,7 +59,50 @@ #endif }
+/* Thermal Trip Points Change Event Handler */ +Method (TPET) +{ #ifdef DPTF_TSR0_SENSOR_ID + Notify (^TSR0, 0x81) +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Notify (^TSR1, 0x81) +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Notify (^TSR2, 0x81) +#endif +#ifdef DPTF_TSR3_SENSOR_ID + Notify (^TSR3, 0x81) +#endif +} + +/* + * Method to return trip temperature value depending upon the device mode. + * Arg0 --> Value to return when device is in tablet mode + * Arg1 --> Value to return when device is not in tablet mode. + */ +Method (DTRP, 2, Serialized) +{ +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + If (LEqual (_SB.PCI0.LPCB.EC0.RCDP, One)) { + Return (CTOK (Arg0)) + } Else { +#endif + Return (CTOK (Arg1)) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + } +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID + +#ifndef DPTF_TSR0_TABLET_PASSIVE +#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE +#endif +#ifndef DPTF_TSR0_TABLET_CRITICAL +#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL +#endif + Device (TSR0) { Name (_HID, EISAID ("INT3403")) @@ -85,12 +128,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR0_PASSIVE)) + Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR0_CRITICAL)) + Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL)) }
Name (PATC, 2) @@ -116,6 +159,14 @@ #endif
#ifdef DPTF_TSR1_SENSOR_ID + +#ifndef DPTF_TSR1_TABLET_PASSIVE +#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE +#endif +#ifndef DPTF_TSR1_TABLET_CRITICAL +#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL +#endif + Device (TSR1) { Name (_HID, EISAID ("INT3403")) @@ -141,12 +192,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR1_PASSIVE)) + Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR1_CRITICAL)) + Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL)) }
Name (PATC, 2) @@ -172,6 +223,14 @@ #endif
#ifdef DPTF_TSR2_SENSOR_ID + +#ifndef DPTF_TSR2_TABLET_PASSIVE +#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE +#endif +#ifndef DPTF_TSR2_TABLET_CRITICAL +#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL +#endif + Device (TSR2) { Name (_HID, EISAID ("INT3403")) @@ -197,12 +256,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR2_PASSIVE)) + Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR2_CRITICAL)) + Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL)) }
Name (PATC, 2) @@ -228,6 +287,14 @@ #endif
#ifdef DPTF_TSR3_SENSOR_ID + +#ifndef DPTF_TSR3_TABLET_PASSIVE +#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE +#endif +#ifndef DPTF_TSR3_TABLET_CRITICAL +#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL +#endif + Device (TSR3) { Name (_HID, EISAID ("INT3403")) @@ -253,12 +320,12 @@
Method (_PSV) { - Return (CTOK (DPTF_TSR3_PASSIVE)) + Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE)) }
Method (_CRT) { - Return (CTOK (DPTF_TSR3_CRITICAL)) + Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL)) }
Name (PATC, 2)