[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust Power State Current 2 threshold

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78653?usp=email )

Change subject: soc/intel/meteorlake: Adjust Power State Current 2 threshold
......................................................................

soc/intel/meteorlake: Adjust Power State Current 2 threshold

VccSA Power State 2 (PS2) current threshold has be adjusted to 10A to
improve PS2 residency which reduces Voltage Regular (VR) power loss.

BUG=b:308002192
TEST=power and performance analysis shows a positive Load Line result

Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865
Signed-off-by: Jeremy Compostella 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78653
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Kapil Porwal 
Reviewed-by: Sukumar Ghorai 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/chipset.cb
M src/soc/intel/meteorlake/romstage/fsp_params.c
3 files changed, 34 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified
  Sukumar Ghorai: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index e860ba97..59b6a8b 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -306,6 +306,30 @@
     */
    uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS];

+	/*
+	 * Power state current threshold 1.
+	 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
+	 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
+	 * SA, [3] through [5] are Reserved.
+	 */
+	uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS];
+
+	/*
+	 * Power state current threshold 2.
+	 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
+	 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
+	 * SA, [3] through [5] are Reserved.
+	 */
+	uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS];
+
+	/*
+	 * Power state current threshold 3.
+	 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512,
+	 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for
+	 * SA, [3] through [5] are Reserved.
+	 */
+	uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS];
+
    uint8_t PmTimerDisabled;
    /*
     * SerialIO device mode selection:
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 69d0df3..865b3d0 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -17,6 +17,10 @@
    # Reduce the size of BasicMemoryTests to speed up the boot time.
    register "lower_basic_mem_test_size" = "true"

+	# The power state current threshold is defined in 1/4 A
+	# increments. A value of 400 = 100A.
+	register "ps_cur_2_threshold[VR_DOMAIN_SA]" = "40" # 10A
+
    # NOTE: if any variant wants to override this value, use the same format
    # as register "common_soc_config.pch_thermal_trip" = "value", instead of
    # putting it under register "common_soc_config" in overridetree.cb file.
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 8f64d4f..2c39bcd 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -238,6 +238,12 @@
    			m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain];
    		}
    	}
+		if (config->ps_cur_1_threshold[domain])
+			m_cfg->Psi1Threshold[domain] = config->ps_cur_1_threshold[domain];
+		if (config->ps_cur_2_threshold[domain])
+			m_cfg->Psi2Threshold[domain] = config->ps_cur_2_threshold[domain];
+		if (config->ps_cur_3_threshold[domain])
+			m_cfg->Psi3Threshold[domain] = config->ps_cur_3_threshold[domain];
    }
 }