[XS] Change in coreboot[main]: mb/google/brask/var/bujia: Disable thunderbolt

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83402?usp=email )

Change subject: mb/google/brask/var/bujia: Disable thunderbolt
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mb/google/brask/var/bujia: Disable thunderbolt

Bujia does not support Thunderbolt anymore,
therefore disable related TBT setting.
The bujia fit image CL, cf. chrome-internal:7468938.

BUG=b:349923139
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot.

Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922
Signed-off-by: Shon 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402
Reviewed-by: Derek Huang 
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 2 insertions(+), 7 deletions(-)

Approvals:
  Derek Huang: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb
index bf60101..61d9525 100644
--- a/src/mainboard/google/brya/variants/bujia/overridetree.cb
+++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb
@@ -151,16 +151,11 @@
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end #NVME
+		device ref tbt_pcie_rp0 off end
    	device ref tbt_pcie_rp1 off end
    	device ref tbt_pcie_rp2 off end

-		device ref tcss_dma0 on
-			chip drivers/intel/usb4/retimer
-				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
-				use tcss_usb3_port1 as dfp[0].typec_port
-				device generic 0 on end
-			end
-		end
+		device ref tcss_dma0 off end
    	device ref tcss_dma1 off end
    	device ref cnvi_wifi on
    		chip drivers/wifi/generic