Change in coreboot[master]: soc/intel/canonlake: Enable UART2 in 32bit PCI mode

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21296

Change subject: soc/intel/canonlake: Enable UART2 in 32bit PCI mode
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soc/intel/canonlake: Enable UART2 in 32bit PCI mode

Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.

Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/21296/3

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index df3cda1..049b2bb 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,7 +60,8 @@
    select CONSOLE_SERIAL
    select BOOTBLOCK_CONSOLE
    select DRIVERS_UART
-	select DRIVERS_UART_8250IO
+	select DRIVERS_UART_8250MEM_32
+	select NO_UART_ON_SUPERIO

config UART_FOR_CONSOLE
    int "Index for LPSS UART port to use for console"