[M] Change in coreboot[master]: soc|vc/amd/phoenix: Prepare for PSP verstage

[Tim Van Patten (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Matt DeVillier, Raul Rangel.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75584?usp=email )

Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage
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Patch Set 1: Code-Review+1

(2 comments)

Patchset:

PS1: 
It looks like there is a lot of overlap with mendocino.

Should we open a bug to collect these files into somewhere each chipset can share? Or are there subtle differences that make that kind of refactor difficult/impossible?

File src/soc/amd/phoenix/psp_verstage/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/75584/comment/3bd79818_3eb1f276 :
PS1, Line 3: ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
`src/soc/amd/mendocino/psp_verstage/Makefile.inc` is slightly different than this. It always builds these files, except for gating `../../common/psp_verstage` with `CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK`.

I would expect this `ifeq` to check `VBOOT_SEPARATE_VERSTAGE`, rather than when vboot runs.