[M] Change in coreboot[main]: arch/riscv: Basic illegal instruction handling

[ron minnich (Code Review)]

Attention is currently required from: Philipp Hug.

Hello Philipp Hug, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81306?usp=email

to look at the new patch set (#11).

Change subject: arch/riscv: Basic illegal instruction handling
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arch/riscv: Basic illegal instruction handling

Add a simple illegal instruction handler, designed for
lowest overhead as opposed to generality.

coreboot SBI is designed to minimize SBI functionality.
This minimization is reflected in the lack of generality
in the code.

On modern RISC-V systems, the trap will not even occur.
At some point RISC-V community figured out that trapping
on reading time was not always the best idea :-)

So, in general, on future systems, reads will not trap.

Signed-off-by: Ronald G Minnich

Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078
---
M src/arch/riscv/trap_handler.c
M src/arch/riscv/virtual_memory.c
2 files changed, 74 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/11