Change in coreboot[master]: soc/intel/skylake: Disable usb2 phy power gating.

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/28074

Change subject: soc/intel/skylake: Disable usb2 phy power gating.
......................................................................

soc/intel/skylake: Disable usb2 phy power gating.

Currently, we found the usb2 phy registers value are restored to soc
default after xhci PS3, PS0 are executed.
This will cause some usb 2.0 devices not detected after xhci resumes
from D3.

Before root cause, this patch temporarily disables the usb2 phy power
gating in xhci PS0 PS3 so that usb2phy registers won't be restored to
soc default.

BUG=b:110175562
TEST=check usb2 phy registers are not gone.

Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d
Signed-off-by: Kane Chen 
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 0 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28074/1

diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 29367de..926f6ac 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -149,24 +149,6 @@

/* Disable USB2 PHY SUS Well Power Gating */
    	Store (Zero, ^UPSW)
-
-		/*
-		 * Apply USB2 PHPY Power Gating workaround if needed.
-		 */
-		If (^^PMC.UWAB) {
-			/* Write to MTPMC to have PMC disable power gating */
-			Store (1, ^^PMC.MPMC)
-
-			/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
-			Store (10, Local0)
-			While (^^PMC.PMFS) {
-				If (LNot (Local0)) {
-					Break
-				}
-				Decrement (Local0)
-				Sleep (10)
-			}
-		}
    }

Method (_PS3, 0, Serialized)
@@ -202,26 +184,6 @@
    	Store (3, Local0)
    	Store (Local0, ^D0D3)
    	Store (^D0D3, Local0)
-
-		/*
-		 * Apply USB2 PHPY Power Gating workaround if needed.
-		 * This code assumes XDCI is disabled, if it is enabled
-		 * then this must also check if it is in D3 state too.
-		 */
-		If (^^PMC.UWAB) {
-			/* Write to MTPMC to have PMC enable power gating */
-			Store (3, ^^PMC.MPMC)
-
-			/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
-			Store (10, Local0)
-			While (^^PMC.PMFS) {
-				If (LNot (Local0)) {
-					Break
-				}
-				Decrement (Local0)
-				Sleep (10)
-			}
-		}
    }

/* Root Hub for Skylake-LP PCH */