Change in ...coreboot[master]: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32915
Change subject: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) ......................................................................
{apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001'
Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 3 files changed, 0 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..9ab4af1 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -140,9 +140,6 @@
static void rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 0c7c0cf..8c0b3e4 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,9 +74,6 @@
static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 502eac3..2404fb7 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -74,9 +74,6 @@
static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321;
Hello Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32915
to look at the new patch set (#2).
Change subject: mb/{i945}: Remove 2nd write to RCBA32(V0CTL) ......................................................................
mb/{i945}: Remove 2nd write to RCBA32(V0CTL)
i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001'
Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 6 files changed, 0 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/2
Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32915
to look at the new patch set (#3).
Change subject: mb/{i945}: Remove 2nd write to RCBA32(V0CTL) ......................................................................
mb/{i945}: Remove 2nd write to RCBA32(V0CTL)
i945/early_init.c already set 'RCBA32(V0CTL) = 0x80000001'
Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 6 files changed, 0 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/3
Hello Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32915
to look at the new patch set (#6).
Change subject: mb/{i945}: Remove 2nd write to RCBA32(V0CTL) ......................................................................
mb/{i945}: Remove 2nd write to RCBA32(V0CTL)
The write on this register is already done here: 'i945/early_init.c'
Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c 5 files changed, 0 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/6
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32915 )
Change subject: mb/{i945}: Remove 2nd write to RCBA32(V0CTL) ......................................................................
Abandoned
https://review.coreboot.org/c/coreboot/+/36877
-
HAOUAS Elyes (Code Review)