Change in coreboot[master]: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS docuemnt number and chapter number
Tiger Lake specific changes will follow in subsequent patches. 1. FSP-M related UPD overrides
"The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 4 files changed, 219 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/1
diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc new file mode 100644 index 0000000..3419e72 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c new file mode 100644 index 0000000..083b998 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* TODO: Update with UPD override as FSP matures */ +} diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c new file mode 100644 index 0000000..1297caa --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c new file mode 100644 index 0000000..1a9f7a8 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include <device/device.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +}
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 15: : #include <assert.h> : #include <console/console.h> unused
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 26: #include <soc/pci_devs.h> unused.
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/systemagent.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 22: #include <device/device.h> unused?
Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36552
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS docuemnt number and chapter number 7. Add required headers into include/soc/ from ICL directory
Tiger Lake specific changes will follow in subsequent patches. 1. FSP-M related UPD overrides
"The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/pch.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 8 files changed, 410 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/2/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/2/src/soc/intel/tigerlake/inc... PS2, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 15: : #include <assert.h> : #include <console/console.h>
unused
Done
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 26: #include <soc/pci_devs.h>
unused.
Done
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/systemagent.c:
https://review.coreboot.org/c/coreboot/+/36552/1/src/soc/intel/tigerlake/rom... PS1, Line 22: #include <device/device.h>
unused?
Done
Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36552
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory
Tiger Lake specific changes will follow in subsequent patches. 1. FSP-M related UPD overrides
"The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/pch.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 8 files changed, 410 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 4: Code-Review-2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... PS4, Line 26: enum board_type { looks like this is usually passed to m_cfg->UserBd, however that is FSP specific and must be present in the corresponsing FSP-M header. Most values aren't even used on Icelake.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 4:
Patch Set 4: Code-Review-2
(1 comment)
just wondering if -2 is for review comments in romstage.h
Hello Raj Astekar, Patrick Rudolph, Aaron Durbin, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36552
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory
Tiger Lake specific changes will follow in subsequent patches. 1. FSP-M related UPD overrides
"The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/pch.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 8 files changed, 402 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/5/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/5/src/soc/intel/tigerlake/inc... PS5, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... PS4, Line 26: enum board_type {
looks like this is usually passed to m_cfg->UserBd, however that is FSP specific and must be present […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... PS4, Line 26: enum board_type {
Most values aren't even used on Icelake.
Please refer to https://github.com/coreboot/coreboot/blob/08aeda6c14886d39e04382c7fe6d24c4b4...
https://github.com/coreboot/coreboot/blob/08aeda6c14886d39e04382c7fe6d24c4b4...
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5: -Code-Review
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... PS4, Line 26: enum board_type {
Most values aren't even used on Icelake. […]
I don't see the enum in FspmUpd.h. Can you please add it on all (future) FspmUpd.h.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/4/src/soc/intel/tigerlake/inc... PS4, Line 26: enum board_type {
I don't see the enum in FspmUpd.h. Can you please add it on all (future) FspmUpd.h.
okay, will make the checkin in FSP code
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 5: Code-Review+2
See my comment on earlier patchset about not moving things around for acpibase/gpe init. In general, let's start with a copy of icelake soc and follow up with cleanups to ensure that any/all differences for tigerlake soc are addressed. This is good as an initial setup.
Hello Raj Astekar, Patrick Rudolph, Aaron Durbin, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36552
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/pch.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 8 files changed, 341 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36552/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... PS6, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 6: Code-Review+2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 6:
(5 comments)
Please provide the correct headers first.
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... PS6, Line 21: FSPM_UPD non existent header
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 19: FSPM_UPD defined in non existent header
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 42: CONTROLLER_INFO defined in non existent header
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 43: CHANNEL_INFO defined in non existent header
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 47: MEMORY_INFO_DATA_HOB defined in non existent header
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/inc... PS6, Line 21: FSPM_UPD
non existent header
this should be handled with FSP header upload CL as Ravi already submitted.
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 19: FSPM_UPD
defined in non existent header
this should be handled with FSP header upload CL as Ravi already submitted.
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 42: CONTROLLER_INFO
defined in non existent header
this should be handled with FSP header upload CL as Ravi already submitted.
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 43: CHANNEL_INFO
defined in non existent header
same
https://review.coreboot.org/c/coreboot/+/36552/6/src/soc/intel/tigerlake/rom... PS6, Line 47: MEMORY_INFO_DATA_HOB
defined in non existent header
same
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 6:
https://review.coreboot.org/c/coreboot/+/36243 CL i mean
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/7/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/7/src/soc/intel/tigerlake/inc... PS7, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 7: Code-Review+1
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 7: Code-Review+2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 7: Code-Review+2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36552/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/36552/8/src/soc/intel/tigerlake/inc... PS8, Line 21: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV)
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
Patch Set 8: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36552 )
Change subject: soc/intel/tigerlake/romstage: Do initial SoC commit till romstage ......................................................................
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/intel/tigerlake/include/soc/romstage.h A src/soc/intel/tigerlake/include/soc/soc_chip.h A src/soc/intel/tigerlake/include/soc/systemagent.h A src/soc/intel/tigerlake/romstage/Makefile.inc A src/soc/intel/tigerlake/romstage/fsp_params.c A src/soc/intel/tigerlake/romstage/pch.c A src/soc/intel/tigerlake/romstage/romstage.c A src/soc/intel/tigerlake/romstage/systemagent.c 8 files changed, 341 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rizwan Qureshi: Looks good to me, approved Arthur Heymans: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Ronak Kanabar: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h new file mode 100644 index 0000000..046e856 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void pch_init(void); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h new file mode 100644 index 0000000..3b02386 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ +#define _SOC_TIGERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h new file mode 100644 index 0000000..56a2bd8 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H +#define SOC_TIGERLAKE_SYSTEMAGENT_H + +#include <intelblocks/systemagent.h> + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define BIOS_RESET_CPL 0x5da8 +#define EDRAMBAR 0x5408 +#define REGBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +#endif diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc new file mode 100644 index 0000000..8d151e3 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c new file mode 100644 index 0000000..810cff4 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <soc/romstage.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* TODO: Update with UPD override as FSP matures */ +} diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c new file mode 100644 index 0000000..88a7cc7 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/smbus.h> +#include <intelblocks/tco.h> +#include <soc/romstage.h> + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c new file mode 100644 index 0000000..17efc98 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c new file mode 100644 index 0000000..183089e --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +}
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