Hello Srinidhi N Kaushik, Raj Astekar, Subrata Banik, Nick Vaccaro, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38622
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: pin mux for ISH ......................................................................
mb/intel/tglrvp: pin mux for ISH
pin mux for ISHUART0, ISHI2C0, ISHGPIO0-7 TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable, PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD value is disabled, FSP doesn't do pin mux.
BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/38622/3