Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45390 )
Change subject: nb/intel/x4x: Relocate read to TPM base address ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45390/4/src/northbridge/intel/x4x/r... File src/northbridge/intel/x4x/raminit.c:
https://review.coreboot.org/c/coreboot/+/45390/4/src/northbridge/intel/x4x/r... PS4, Line 621: read8((void *)TPM_BASE_ADDRESS);
you don't use the information gathered, so this is as useless as before.
On Haswell with a TXT-capable CPU/PCH and no TPM, if I don't perform any reads to the TPM access register, raminit will fail. A single read is enough to unblock the memory. (Yes, an extra MSR 0x2e6 write is needed, but that would fail if I didn't read the TPM access register beforehand.
I recall reading somewhere that the MCH will always unblock the memory if a read to the access register returns a one in bit 0 (TPM establishment not asserted). Sure, that isn't being checked here, but without a TPM this always returns 0xff