[coreboot-gerrit] Change in coreboot[master]: intel/e7505: Always enable DIMM compatibility checks

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38295 )

Change subject: intel/e7505: Always enable DIMM compatibility checks
......................................................................

intel/e7505: Always enable DIMM compatibility checks

Change-Id: I4862b4f0a029f6f4a1ff7e66cf814fa8f5686d3f
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38295
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/e7505/raminit.c
1 file changed, 2 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 517ba6f..72f630d 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -48,11 +48,6 @@
 Definitions:
 -----------------------------------------------------------------------------*/

-// Uncomment this to enable run-time checking of DIMM parameters
-// for dual-channel operation
-// Unfortunately the code seems to chew up several K of space.
-//#define VALIDATE_DIMM_COMPATIBILITY
-
 #if CONFIG(DEBUG_RAM_SETUP)
 #define RAM_DEBUG_MESSAGE(x)	printk(BIOS_DEBUG, x)
 #define RAM_DEBUG_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
@@ -115,7 +110,6 @@

#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)

-#ifdef VALIDATE_DIMM_COMPATIBILITY
 // SPD parameters that must match for dual-channel operation
 static const uint8_t dual_channel_parameters[] = {
    SPD_MEMORY_TYPE,
@@ -126,7 +120,6 @@
    SPD_PRIMARY_SDRAM_WIDTH,
    SPD_NUM_BANKS_PER_SDRAM
 };
-#endif /* VALIDATE_DIMM_COMPATIBILITY */

/* Comments here are remains of e7501 or even 855PM.
     * They might be partially (in)correct for e7505.
@@ -465,8 +458,6 @@
    return sz;
 }

-#ifdef VALIDATE_DIMM_COMPATIBILITY
-
 /**
  * Determine whether two DIMMs have the same value for an SPD parameter.
  *
@@ -490,7 +481,6 @@

return bEqual;
 }
-#endif

/**
  * Scan for compatible DIMMs.
@@ -527,10 +517,8 @@
    	uint16_t channel0_dimm = ctrl->channel0[i];
    	uint16_t channel1_dimm = ctrl->channel1[i];
    	uint8_t bDualChannel = 1;
-#ifdef VALIDATE_DIMM_COMPATIBILITY
    	struct dimm_size page_size;
    	struct dimm_size sdram_width;
-#endif
    	int spd_value;

if (channel0_dimm == 0)
@@ -540,7 +528,6 @@
    	    SPD_MEMORY_TYPE_SDRAM_DDR)
    		continue;

-#ifdef VALIDATE_DIMM_COMPATIBILITY
    	if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
    	    SPD_VOLTAGE_SSTL2)
    		continue;	// Unsupported voltage
@@ -586,7 +573,7 @@
    		    && (sdram_width.side2 != 8))
    			continue;
    	}
-#endif
+
    	// Channel 0 DIMM looks compatible.
    	// Now see if it is paired with the proper DIMM on channel 1.

@@ -599,7 +586,7 @@
    		printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
    		continue;
    	}
-#ifdef VALIDATE_DIMM_COMPATIBILITY
+
    	spd_value = smbus_read_byte(channel1_dimm,
    			  SPD_SUPPORTED_BURST_LENGTHS);
    	if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
@@ -615,7 +602,6 @@
    			break;
    		}
    	}
-#endif /* VALIDATE_DIMM_COMPATIBILITY */

if (bDualChannel) {
    		// This DIMM pair is usable