Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46769 )
Change subject: mb/google/auron: Move SATA PCI device to overridetree ......................................................................
mb/google/auron: Move SATA PCI device to overridetree
`chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope.
Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip.
TEST=Sanity-check static.c and verify variant overrides are used.
Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb 7 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46769/1
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7..79bb8b0 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -80,7 +80,6 @@ device pnp 0c09.0 on end end end # LPC bridge - device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal # end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index dc70085..f5f3eea 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index b46e34c..5a64648 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 45229ba..5b6ab9f 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -34,6 +34,7 @@ device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus # end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index eae7999..924e7d3 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index dc70085..f5f3eea 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -12,6 +12,8 @@ # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 710fa95..9344575 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,6 +36,7 @@ device pci 1c.0 off end # PCIe Port #1 device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI + device pci 1f.2 on end # SATA Controller # end end end