[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add VrPowerDeliveryDesign to chip options

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63303 )

Change subject: soc/intel/alderlake: Add VrPowerDeliveryDesign to chip options
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soc/intel/alderlake: Add VrPowerDeliveryDesign to chip options

The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.

Signed-off-by: Lean Sheng Tan 
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63303/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a69e645..1e59018 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -441,6 +441,13 @@
    uint8_t dmi_power_optimize_disable;

/*
+	 * Used to communicate the power delivery design capability of the board. This
+	 * value is an enum of the available power delivery segments that are defined in
+	 * the Platform Design Guide.
+	 */
+	uint8_t VrPowerDeliveryDesign;
+
+	/*
     * Enable(1)/Disable(0) CPU Replacement check.
     * Default 0. Setting this to 1 to check CPU replacement.
     */
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd2c0be..70ceac5 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -748,6 +748,8 @@
    }

s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
+
+	s_cfg->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
 }

static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,