[coreboot-gerrit] Change in coreboot[master]: southbridge/intel/wildcatpoint: Add header files

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41938

to look at the new patch set (#16).

Change subject: southbridge/intel/wildcatpoint: Add header files
......................................................................

southbridge/intel/wildcatpoint: Add header files

Relocate southbridge-related headers from soc to the southbridge scope.
Note that the code in soc/intel/common expects to find `soc/nvs.h`.

And yes, some prototypes are now in the wrong place. This will be fixed
in the next commits, once the soc/intel/broadwell subfolder is no more.

With BUILD_TIMELESS=1 but without adding the .config file into the
resulting coreboot image, google/auron (Buddy) remains identical.

Change-Id: If2bdef9b44ec8c93c1469074dc51a9964b4101ce
Signed-off-by: Angel Pons 
---
M src/cpu/intel/broadwell/acpi.c
M src/cpu/intel/broadwell/bootblock.c
M src/cpu/intel/broadwell/chip.c
M src/cpu/intel/broadwell/cpu.c
M src/cpu/intel/broadwell/romstage.c
M src/cpu/intel/broadwell/smmrelocate.c
M src/mainboard/google/auron/acpi_tables.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/auron/variants/auron_paine/gpio.c
M src/mainboard/google/auron/variants/auron_paine/pei_data.c
M src/mainboard/google/auron/variants/auron_paine/spd/spd.c
M src/mainboard/google/auron/variants/auron_yuna/gpio.c
M src/mainboard/google/auron/variants/auron_yuna/pei_data.c
M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
M src/mainboard/google/auron/variants/buddy/gpio.c
M src/mainboard/google/auron/variants/buddy/pei_data.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/auron/variants/gandof/gpio.c
M src/mainboard/google/auron/variants/gandof/pei_data.c
M src/mainboard/google/auron/variants/gandof/spd/spd.c
M src/mainboard/google/auron/variants/gandof/variant.c
M src/mainboard/google/auron/variants/lulu/gpio.c
M src/mainboard/google/auron/variants/lulu/pei_data.c
M src/mainboard/google/auron/variants/lulu/spd/spd.c
M src/mainboard/google/auron/variants/lulu/variant.c
M src/mainboard/google/auron/variants/samus/gpio.c
M src/mainboard/google/auron/variants/samus/pei_data.c
M src/mainboard/google/auron/variants/samus/spd/spd.c
M src/mainboard/google/auron/variants/samus/variant.c
M src/mainboard/google/jecht/acpi_tables.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/jecht/smihandler.c
M src/mainboard/google/jecht/variants/guado/gpio.c
M src/mainboard/google/jecht/variants/guado/pei_data.c
M src/mainboard/google/jecht/variants/jecht/gpio.c
M src/mainboard/google/jecht/variants/jecht/pei_data.c
M src/mainboard/google/jecht/variants/rikku/gpio.c
M src/mainboard/google/jecht/variants/rikku/pei_data.c
M src/mainboard/google/jecht/variants/tidus/gpio.c
M src/mainboard/google/jecht/variants/tidus/pei_data.c
M src/mainboard/intel/wtm2/acpi_tables.c
M src/mainboard/intel/wtm2/chromeos.c
M src/mainboard/intel/wtm2/gpio.c
M src/mainboard/intel/wtm2/pei_data.c
M src/mainboard/intel/wtm2/romstage.c
M src/mainboard/purism/librem_bdw/acpi_tables.c
M src/mainboard/purism/librem_bdw/gpio.c
M src/northbridge/intel/broadwell/acpi/broadwell.asl
M src/northbridge/intel/broadwell/bootblock.c
M src/northbridge/intel/broadwell/broadwell.h
M src/northbridge/intel/broadwell/finalize.c
M src/northbridge/intel/broadwell/igd.c
M src/northbridge/intel/broadwell/memmap.c
M src/northbridge/intel/broadwell/minihd.c
M src/northbridge/intel/broadwell/pei_data.c
M src/northbridge/intel/broadwell/raminit.c
M src/northbridge/intel/broadwell/refcode.c
M src/northbridge/intel/broadwell/report_platform.c
M src/northbridge/intel/broadwell/romstage.c
M src/northbridge/intel/broadwell/systemagent.c
D src/soc/intel/broadwell/include/soc/cpu.h
M src/soc/intel/broadwell/include/soc/nvs.h
M src/soc/intel/broadwell/include/soc/systemagent.h
R src/southbridge/intel/wildcatpoint/acpi.h
M src/southbridge/intel/wildcatpoint/acpi/pch.asl
M src/southbridge/intel/wildcatpoint/adsp.c
R src/southbridge/intel/wildcatpoint/adsp.h
M src/southbridge/intel/wildcatpoint/bootblock.c
R src/southbridge/intel/wildcatpoint/device_nvs.h
M src/southbridge/intel/wildcatpoint/early_pch.c
M src/southbridge/intel/wildcatpoint/early_smbus.c
M src/southbridge/intel/wildcatpoint/ehci.c
R src/southbridge/intel/wildcatpoint/ehci.h
M src/southbridge/intel/wildcatpoint/elog.c
M src/southbridge/intel/wildcatpoint/gpio.c
R src/southbridge/intel/wildcatpoint/gpio.h
M src/southbridge/intel/wildcatpoint/hda.c
M src/southbridge/intel/wildcatpoint/iobp.c
R src/southbridge/intel/wildcatpoint/iobp.h
R src/southbridge/intel/wildcatpoint/iomap.h
M src/southbridge/intel/wildcatpoint/lpc.c
R src/southbridge/intel/wildcatpoint/lpc.h
M src/southbridge/intel/wildcatpoint/me.c
R src/southbridge/intel/wildcatpoint/me.h
M src/southbridge/intel/wildcatpoint/me_status.c
A src/southbridge/intel/wildcatpoint/nvs.h
M src/southbridge/intel/wildcatpoint/pch.c
R src/southbridge/intel/wildcatpoint/pch.h
R src/southbridge/intel/wildcatpoint/pci_devs.h
M src/southbridge/intel/wildcatpoint/pcie.c
R src/southbridge/intel/wildcatpoint/pm.h
M src/southbridge/intel/wildcatpoint/pmutil.c
M src/southbridge/intel/wildcatpoint/power_state.c
M src/southbridge/intel/wildcatpoint/ramstage.c
R src/southbridge/intel/wildcatpoint/ramstage.h
R src/southbridge/intel/wildcatpoint/rcba.h
M src/southbridge/intel/wildcatpoint/sata.c
R src/southbridge/intel/wildcatpoint/sata.h
M src/southbridge/intel/wildcatpoint/serialio.c
R src/southbridge/intel/wildcatpoint/serialio.h
M src/southbridge/intel/wildcatpoint/smbus.c
R src/southbridge/intel/wildcatpoint/smbus.h
M src/southbridge/intel/wildcatpoint/smi.c
M src/southbridge/intel/wildcatpoint/smihandler.c
R src/southbridge/intel/wildcatpoint/soc_chip.h
R src/southbridge/intel/wildcatpoint/spi.h
M src/southbridge/intel/wildcatpoint/uart.c
M src/southbridge/intel/wildcatpoint/xhci.c
R src/southbridge/intel/wildcatpoint/xhci.h
111 files changed, 272 insertions(+), 271 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41938/16