[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add Rcomp data structure

[Srinidhi N Kaushik (Code Review)]

Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39040

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: add Rcomp data structure
......................................................................

soc/intel/tigerlake: add Rcomp data structure

Add Rcomp data structure in meminit to support updating rcomp resistor
and target values for DDR4 support.

BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I3858cc56c838862fc61123c8b7dba11dbc40983c
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39040/3