[coreboot-gerrit] Change in coreboot[master]: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35161 )

Change subject: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP
......................................................................

arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP

Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.

This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.

BUG=b:140250314

Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Arthur Heymans 
---
M src/arch/x86/postcar_loader.c
1 file changed, 0 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 6a7d389..61a9d52 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -125,9 +125,6 @@
    if (pcf->skip_common_mtrr)
    	return;

-	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
-	postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
    /* Cache the ROM as WP just below 4GiB. */
    postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
 }