Attention is currently required from: Hung-Te Lin, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49819 )
Change subject: TEST-ONLY: dramc: mt8192: change architecture ......................................................................
Patch Set 1:
(90 comments)
File src/soc/mediatek/common/dramc/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/49819/comment/8ee95fdf_7722467c PS1, Line 218: trailing whitespace
https://review.coreboot.org/c/coreboot/+/49819/comment/6fdc22ab_9df066da PS1, Line 221: trailing whitespace
https://review.coreboot.org/c/coreboot/+/49819/comment/5532b7d9_2d54b098 PS1, Line 282: /* set avaiable voltage for the cali */ 'avaiable' may be misspelled - perhaps 'available'?
https://review.coreboot.org/c/coreboot/+/49819/comment/7acbd209_1c0cc523 PS1, Line 315: dramc_info("%u Mbps calibration finish\n", get_frequency(cali) * DRAMC_DDR_MULTIPLE); line over 96 characters
File src/soc/mediatek/common/dramc/dramc_power.c:
https://review.coreboot.org/c/coreboot/+/49819/comment/6cb613c5_5a24ca0c PS1, Line 173: else { else is not generally useful after a break or return
File src/soc/mediatek/common/dramc/include/soc/dramc_common.h:
https://review.coreboot.org/c/coreboot/+/49819/comment/6c04d1cf_a70c6e9a PS1, Line 6: /* trailing whitespace
https://review.coreboot.org/c/coreboot/+/49819/comment/b049c07f_5f05bd95 PS1, Line 10: * By default: MAX CHANNLE: 2, MAX RANK: 2, MAX FSP: 2. 'CHANNLE' may be misspelled - perhaps 'CHANNEL'?
File src/soc/mediatek/common/dramc/include/soc/dramc_ops.h:
https://review.coreboot.org/c/coreboot/+/49819/comment/66bafda4_80196b7e PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/5baa00ad_705125fd PS1, Line 2: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/9402db6b_1a841a37 PS1, Line 3: #ifndef SOC_MEDIATEK_DRAMC_OPS_H DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/aa250f73_5e1e0127 PS1, Line 4: #define SOC_MEDIATEK_DRAMC_OPS_H DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/67378216_420f9483 PS1, Line 5: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/c0277db1_3bacb524 PS1, Line 6: #include <soc/dramc_common.h> DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/5f4da932_d199466d PS1, Line 7: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ae71b627_91143417 PS1, Line 8: struct ddr_cali; DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ec3e9825_3f14e1cc PS1, Line 9: struct emi_mdl; DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/40c5383d_63e773ee PS1, Line 10: struct dram_impedance; DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/af81b494_864dc991 PS1, Line 11: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/a8f27cd8_7b777d10 PS1, Line 12: typedef struct dramc_cal_ops { DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/f1a83341_3ad082a2 PS1, Line 13: /* boradcast for multi channel */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/f6b68002_bf232542 PS1, Line 14: u32 (*get_broadcast)(void); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/e958806f_25705846 PS1, Line 15: void (*set_broadcast)(u32 onoff); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ca2f0ab9_dfed7280 PS1, Line 16: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/99848bad_ba21836b PS1, Line 17: /* memory pll */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/04445aca_8650e976 PS1, Line 18: u32 (*mpll_init)(void); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/abc7a545_74d4f97e PS1, Line 19: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/a7100427_f6ccde2b PS1, Line 20: /* pinmux */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/e30494f3_e66df638 PS1, Line 21: void (*get_dram_pinmux)(struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/6eac0695_209118c1 PS1, Line 22: void (*set_mrr_pinmux_mapping)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/a1534f8b_7ac6fe3a PS1, Line 23: void (*set_dqo1_pinmux_mapping)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/d7e563bf_d58f6ed7 PS1, Line 24: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/33378315_64128531 PS1, Line 25: /* EMI */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ead75a8d_2a9b5d16 PS1, Line 26: void (*emi_mdl_init)(const struct emi_mdl *emi_con); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/1d3d3299_d8d4261e PS1, Line 27: void (*emi_init_before_first_cal)(void); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/f56ac215_57f83446 PS1, Line 28: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/89d4c287_d99382bf PS1, Line 29: /* FSP */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/b8504a55_1932de00 PS1, Line 30: u8 (*get_fsp_by_freq)(dram_freq_grp freq_grp); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/db696c3e_8002c5d1 PS1, Line 31: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/feb902f2_705cc60c PS1, Line 32: /* DBI */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/af3ef388_6cdbd451 PS1, Line 33: void (*update_wdbi_on_off)(struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/fd1f3029_3d2428aa PS1, Line 34: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/67d005ce_598fa6af PS1, Line 35: /* ODT */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/3faec310_37a472da PS1, Line 36: dram_odt_state (*update_odt_on_off)(struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/3cadf02e_a055e21f PS1, Line 37: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/fa4707fe_99cd5ebc PS1, Line 38: /* cali struct init, if NULL, use default */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/1c1f418b_761af993 PS1, Line 39: void (*init_ddr_cali_struct)(struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/702c8e80_d40bbe64 PS1, Line 40: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/de0b3324_8e02c36b PS1, Line 41: /* save dram info to registers */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/97e3dfd7_0a791da5 PS1, Line 42: void (*set_dram_info_to_conf)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/447a83da_19f3a38f PS1, Line 43: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/79ca4772_2db690ba PS1, Line 44: /* impedance */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/838e90a2_eb4b1daa PS1, Line 45: void (*sw_impedance_cal)(dram_odt_state odt, DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/506fbd38_4203e1de PS1, Line 46: struct dram_impedance *imp); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/feb5f2b6_9929efb8 PS1, Line 47: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/eafea4d0_3cc4dcd5 PS1, Line 48: /* trailing whitespace
https://review.coreboot.org/c/coreboot/+/49819/comment/5d8aa535_a443eff9 PS1, Line 49: * dram voltage trailing whitespace
https://review.coreboot.org/c/coreboot/+/49819/comment/5b5a9eff_642d037c PS1, Line 50: */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/e38849ac_f5960e20 PS1, Line 51: void (*set_vcore_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/75cd7a63_01ce0ff1 PS1, Line 52: void (*set_vdd1_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/987f0a4d_afd46a23 PS1, Line 53: void (*set_vdd2_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/8699056f_d9247603 PS1, Line 54: void (*set_vddq_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/cb1eee70_2e0dc48f PS1, Line 55: void (*set_vmddr_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/49837ebe_5b283fc3 PS1, Line 56: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/b681a2ee_da171e77 PS1, Line 57: u32 (*get_vcore_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/248f5382_82a48690 PS1, Line 58: u32 (*get_vdd1_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/b41d517e_c4500d13 PS1, Line 59: u32 (*get_vdd2_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ae377e63_6557e4ef PS1, Line 60: u32 (*get_vddq_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/e0f0d06a_0f6c7190 PS1, Line 61: u32 (*get_vmddr_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/6fd45d09_66674beb PS1, Line 62: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/832c99a2_82e148e3 PS1, Line 63: u32 (*get_vcore_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/ecf8f46b_1dada212 PS1, Line 64: u32 (*get_vdd1_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/e33f835c_652561c4 PS1, Line 65: u32 (*get_vdd2_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/a137c315_d23bbcf6 PS1, Line 66: u32 (*get_vddq_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/b059706f_cf040171 PS1, Line 67: u32 (*get_vmddr_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/976669aa_67864c72 PS1, Line 68: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/56ed360b_3d07d72e PS1, Line 69: /* set dram related volatage except VCORE, eg: VDD1/VDD2/VDDQ/VMDDR */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/a8fe5566_20013f07 PS1, Line 70: void (*set_dram_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/608b3598_5722bbe4 PS1, Line 71: void (*dump_dram_voltage)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/cfbf7e19_bed88805 PS1, Line 72: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/d200f6ca_81d5d5f1 PS1, Line 73: /* dramc init */ DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/db30ca69_0ea65292 PS1, Line 74: void (*init_default_mr_value)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/83dcb13f_e5db2de7 PS1, Line 75: void (*init)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/89289ec5_a0c08839 PS1, Line 76: void (*init_before_calibration)(const struct ddr_cali *cali); DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/302b2e19_0fae4855 PS1, Line 77: } dramc_cal_ops; DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/d9cc2625_ccdd1fa1 PS1, Line 78: DOS line endings
https://review.coreboot.org/c/coreboot/+/49819/comment/7514f190_15403d1b PS1, Line 79: #endif DOS line endings
File src/soc/mediatek/mt8192/mem_init.c:
https://review.coreboot.org/c/coreboot/+/49819/comment/23cc7e03_54dd9d39 PS1, Line 178: return (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; Statements should start on a tabstop
https://review.coreboot.org/c/coreboot/+/49819/comment/9edd60e8_37bd6aa9 PS1, Line 5049: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t); line over 96 characters
https://review.coreboot.org/c/coreboot/+/49819/comment/4c50ec35_a76cfe39 PS1, Line 5052: SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); line over 96 characters
https://review.coreboot.org/c/coreboot/+/49819/comment/c629413d_774961fd PS1, Line 5170: trailing whitespace