Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46419 )
Change subject: mb/intel/adlrvp: Enable PCIE RP11 for optane ......................................................................
mb/intel/adlrvp: Enable PCIE RP11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device uses RP9 - NVMe Optane memory uses RP11
Note: These two devices are sharing CLK PINs.
TEST=Build and boot ADL RVP board using Intel Optane card.
Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46419/1
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index afa4c19..fadf602 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -59,6 +59,9 @@ register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1"
+ # Enable PCH PCIE RP 11 for optane + register "PcieRpEnable[10]" = "1" + # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40"
@@ -241,7 +244,7 @@ device pci 1c.7 off end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 - device pci 1d.2 off end # RP11 + device pci 1d.2 on end # RP11 device pci 1d.3 off end # RP12 device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1