[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apl, cnl, skl}: Add sanity check of SA_PCIEX_LENGTH_MIB

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40337 )

Change subject: soc/intel/{apl, cnl, skl}: Add sanity check of SA_PCIEX_LENGTH_MIB
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40337/1/src/soc/intel/skylake/syste... 
File src/soc/intel/skylake/systemagent.c:

https://review.coreboot.org/c/coreboot/+/40337/1/src/soc/intel/skylake/syste... 
PS1, Line 17: #if (CONFIG_SA_PCIEX_LENGTH_MIB > 0x100) /* Max length is 256MB */
            : #error "Invalid SA_PCIEX_LENGTH_MIB selection!"
            : #endif
> Yes, looking at EDS, it appears that maximum PCIEXBAR length support for SKL/KBL is 256MB. […]

Yes you are right. It seemed to me that xeon e3 might be different from other skl/kbl cpus. Thanks