Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46069 )
Change subject: mb/google/volteer/var/voxel: disable DdiPortHpd ......................................................................
mb/google/volteer/var/voxel: disable DdiPortHpd
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd
BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46069/1
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 330d852..f3a04b4 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" register "tcc_offset" = "5" # TCC of 95
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{