[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update chip files

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded a new patch set (#29) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37783 )

Change subject: soc/intel/tigerlake: Update chip files
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soc/intel/tigerlake: Update chip files

Update chip files to include :
  - Update chip.c based on TGL FSP
  - Update chip.h based on TGL FSP
  - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
  - Update pmc_utils.c and JSL devicetree for build failure

Reference
PCH EDS#576591 vol1 rev1.2

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi 
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/pmutil.c
5 files changed, 73 insertions(+), 93 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37783/29