[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55254 )

Change subject: soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon
......................................................................

soc/intel/alderlake: Corrects PMC Descriptor for Alderlake B silicon

The patch corrects PMC Descriptpr 7 which is part of Descriptor Region
if system having Alderlake B silicon

TEST=Verified PMC Descriptor 7 getting modified for Alderlake B silicon

Signed-off-by: Sridhar Siricilla 
Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 73 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55254/1

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index e6a9592..c0c8732 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -12,8 +12,15 @@
 #include <soc/intel/common/smbios.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <soc/intel/common/reset.h>
+#include <fmap.h>
+#include <commonlib/region.h>
+#include <intelblocks/mp_init.h>
 #include <string.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -22,6 +29,14 @@
    0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
 }

+#define SI_DESC_REGION	"SI_DESC"
+#define SI_DESC_REGION_SZ	4096
+#define PMC_DESC_7_BYTE3	0xc32
+
+#define DESC_REGION_CONFIG_FAIL -1
+#define GLOBAL_RESET_REQUIRED      1
+#define GLOBAL_RESET_IS_NOT_REQUIRED      2
+
 /* Save the DIMM information for SMBIOS table 17 */
 static void save_dimm_info(void)
 {
@@ -114,6 +129,45 @@
    printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }

+static int8_t cse_get_rw_rdev(struct region_device *rdev)
+{
+	if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, rdev) < 0) {
+		printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION);
+		return -1;
+	}
+
+	return 0;
+}
+
+static uint8_t configure_cpu_boot_fivr(void)
+{
+	uint8_t si_desc_buf[SI_DESC_REGION_SZ];
+	struct region_device desc_dev;
+
+	if(cse_get_rw_rdev(&desc_dev) < 0)
+		return DESC_REGION_CONFIG_FAIL;
+
+	if (rdev_readat(&desc_dev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) {
+		printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n");
+		return DESC_REGION_CONFIG_FAIL;
+	}
+
+	if (si_desc_buf[PMC_DESC_7_BYTE3]  == 0x44 ) {
+		si_desc_buf[PMC_DESC_7_BYTE3]  = 0x40;
+
+		if (rdev_writeat(&desc_dev, si_desc_buf, 0, SI_DESC_REGION_SZ)
+			!= SI_DESC_REGION_SZ) {
+			printk(BIOS_ERR, "Failed to update CPU BOOT FIVR strap in the Descriptor Region\n");
+			return DESC_REGION_CONFIG_FAIL;
+		}
+		printk(BIOS_DEBUG, "Update of CPU BOOT FIVR strap successful, trigger GLOBAL RESET\n");
+		return GLOBAL_RESET_REQUIRED;
+	}
+
+	printk(BIOS_DEBUG, "CPU BOOT FIVR configuration is not required!\n");
+	return GLOBAL_RESET_IS_NOT_REQUIRED;
+}
+
 void mainboard_romstage_entry(void)
 {
    bool s3wake;
@@ -129,18 +183,36 @@
    s3wake = pmc_fill_power_state(ps) == ACPI_S3;
    fsp_memory_init(s3wake);
    pmc_set_disb();
+
    if (!s3wake) {
+		uint32_t cpu_id = cpu_get_cpuid();
+		int8_t ret = GLOBAL_RESET_IS_NOT_REQUIRED;
+
+		/*
+		 * If configure_cpu_boot_fivr() requests GLOBAL_RESET,let's do after
+		 * cse_fw_sync().
+		 */
+		if (cpu_id == CPUID_ALDERLAKE_B0)
+			ret = configure_cpu_boot_fivr();
+
    	/*
    	 * cse_fw_sync() must be called after DRAM initialization as
    	 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
    	 * is expected to be executed after DRAM initialization.
    	 * When AP starts from G3, cse_fw_sync() triggers GLOBAL RESET after
    	 * marking CSE's next boot partition to RW. Also, it trigger CSE Firmware update
-		 * if CSE RW blob's version is different from CSE RW version.
+	         * if CSE RW blob's version is different from CSE RW version.
    	 */
    	if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
    		cse_fw_sync();

+		/*
+		 * if configure_cpu_boot_fivr() requests GLOBAL RESET and cse_fw_sync() didn't
+		 * trigger GLOBAL RESET, so trigger GLOBAL RESET here
+		 */
+		if (ret == GLOBAL_RESET_REQUIRED)
+			do_global_reset();
+
    	save_dimm_info();
    }
 }