HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33964
Change subject: cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx ......................................................................
cpu/x86/pae/pgtbl: Use CRx_TYPE type for CRx
Change-Id: I8108398071a6ff7bceb90741581522023a786afd Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33964/1
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index f54a1c3..5d23ce5 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -76,7 +76,7 @@ struct pde pdp[512]; } __packed;
-void paging_enable_pae_cr3(uintptr_t cr3) +void paging_enable_pae_cr3(CRx_TYPE cr3) { /* Load the page table address */ write_cr3(cr3); @@ -198,7 +198,7 @@ /* Get pointer to PD that's not identity mapped */ pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT];
- paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp);
do { const size_t len = MIN(length, s2MiB - offset); @@ -279,7 +279,7 @@ | ((i & 0x3ff) << 21) | 0xE3; pd[i].addr_hi = (window >> 1); } - paging_enable_pae_cr3((uintptr_t)pdp); + paging_enable_pae_cr3((CRx_TYPE)pdp); } mapped_window[index] = window; } @@ -376,7 +376,7 @@ return -1; }
- paging_enable_pae_cr3((uintptr_t)_pdpt); + paging_enable_pae_cr3((CRx_TYPE)_pdpt);
return 0; } diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index 72bae53..6464503 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -22,7 +22,7 @@
/* Enable paging with cr3 value for page directory pointer table as well as PAE option in cr4. */ -void paging_enable_pae_cr3(uintptr_t cr3); +void paging_enable_pae_cr3(CRx_TYPE cr3); /* Enable paging as well as PAE option in cr4. */ void paging_enable_pae(void); /* Disable paging as well as PAE option in cr4. */