[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Update GNVS using common save state accessors

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45762 )

Change subject: soc/intel/baytrail: Update GNVS using common save state accessors
......................................................................

soc/intel/baytrail: Update GNVS using common save state accessors

Change-Id: Ifbb9506cad9949f723f8a2eb05a95c426742a06e
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/baytrail/smihandler.c
1 file changed, 7 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/45762/1

diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index cf47341..1048a3a 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -6,7 +6,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/x86/save_state.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <halt.h>
@@ -152,41 +152,6 @@
 }

/*
- * Look for Synchronous IO SMI and use save state from that core in case
- * we are not running on the same core that initiated the IO transaction.
- */
-static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
-{
-	em64t100_smm_state_save_area_t *state;
-	int node;
-
-	/* Check all nodes looking for the one that issued the IO */
-	for (node = 0; node < CONFIG_MAX_CPUS; node++) {
-		state = smm_get_save_state(node);
-
-		/* Check for Synchronous IO (bit0==1) */
-		if (!(state->io_misc_info & (1 << 0)))
-			continue;
-
-		/* Make sure it was a write (bit4==0) */
-		if (state->io_misc_info & (1 << 4))
-			continue;
-
-		/* Check for APMC IO port */
-		if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
-			continue;
-
-		/* Check AX against the requested command */
-		if ((state->rax & 0xff) != cmd)
-			continue;
-
-		return state;
-	}
-
-	return NULL;
-}
-
-/*
  * soc_legacy: A payload (Depthcharge) has indicated that the
  *   legacy payload (SeaBIOS) is being loaded. Switch devices that are
  *   in ACPI mode to PCI mode so that non-ACPI drivers may work.
@@ -243,7 +208,6 @@
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
-	em64t100_smm_state_save_area_t *state;

/* Emulate B2 register as the FADT / Linux expects it */

@@ -278,10 +242,12 @@
    		printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
    		return;
    	}
-		state = smi_apmc_find_state_save(reg8);
-		if (state) {
-			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
+		int node = get_apmc_node(reg8);
+		if (node >= 0) {
+			if (get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) {
+				printk(BIOS_ERR, "SMI#: ERROR: unable to get GNVS pointer\n");
+				return;
+			}
    		if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
    			printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
    			return;