Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30998 )
Change subject: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout ......................................................................
soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro.
Signed-off-by: Daniel Kurtz djkurtz@chromium.org
BUG=b:113880780 BRANCH=none TEST=compile
Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 04eda49..47eae84 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -462,6 +462,7 @@ #define GPIO_TIMEBASE_15560uS (1 << 7) #define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ GPIO_TIMEBASE_15560uS) +#define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) #define GPIO_IN_60uS (1 | GPIO_TIMEBASE_61uS) #define GPIO_IN_120uS (2 | GPIO_TIMEBASE_61uS) #define GPIO_IN_200uS (3 | GPIO_TIMEBASE_61uS)