Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67770 )
Change subject: soc/intel/alderlake: Fix UFS OCP fabric timeout ......................................................................
soc/intel/alderlake: Fix UFS OCP fabric timeout
The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric.
This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation
BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/acpi/southbridge.asl A src/soc/intel/alderlake/acpi/ufs.asl M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc D src/soc/intel/common/block/scs/ufs.c 6 files changed, 123 insertions(+), 56 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9e41cad..c1acc37 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -67,7 +67,6 @@ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N - select SOC_INTEL_COMMON_UFS_SUPPORT select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE select SYSTEM_TYPE_LAPTOP diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3c37d57..2e419b1 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "scs.asl" #endif
+/* UFS */ +#include "ufs.asl" + /* SMBus 0:1f.4 */ #include <soc/intel/common/block/acpi/acpi/smbus.asl>
diff --git a/src/soc/intel/alderlake/acpi/ufs.asl b/src/soc/intel/alderlake/acpi/ufs.asl new file mode 100644 index 0000000..d6774f8 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/ufs.asl @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pcr_ids.h> + +#define R_SCS_CFG_PCS 0x84 +#define R_SCS_CFG_PG_CONFIG 0xA2 + +#define PID_UFSX2 0x50 + +#define R_SCS_PCR_1C20 0x1C20 +#define R_SCS_PCR_4820 0x4820 +#define R_SCS_PCR_4020 0x4020 +#define R_SCS_PCR_5820 0x5820 +#define R_SCS_PCR_5C20 0x5C20 +#define R_SCS_PCR_1078 0x1078 +#define R_PMC_PWRM_LTR_IGN 0x1B0C + +External(PCRA, MethodObj) + +Scope (_SB.PCI0) +{ + Device (UFS) + { + Name (_ADR, 0x0000000000120007) // _ADR: Address + Name (_DDN, "UFS Controller") // _DDN: DOS Device Name + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, + Package (0x01) + { + Package (0x02) + { + "ref-clk-freq", + CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ + } + } + }) + + Method (OCPD, 0, Serialized) + { + + /* + * OCP Timer need to be disabled in SCS UFS IOSF Bridge to work around + * the Silicon Issue due to which LTR mechanism doest work Registers + * from the UFS OCP Fabric Register space that need to be programmed + * for the timeout are + * Upstream Initiator Port -- offset 0x4020 + * Downstream Target Port -- offset 0x4820 + * Downstream Target port at Controller -- offset 0x5c20 + * Upstream Initiator port at Controller -- offset 0x5820 + * Control over interconnect-wide functions -- offset 0x1078 + */ + PCRA (PID_UFSX2, R_SCS_PCR_4020, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_4820, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_5C20, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_5820, 0x0) + PCRA (PID_UFSX2, R_SCS_PCR_1078, 0x0) + } + + /* Memory Region to access to the UFS PCI Configuration Space */ + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field (SCSR, ByteAcc, NoLock, Preserve) + { + Offset(R_SCS_CFG_PCS), /* 0x84, PMCSR - Power Management Control and Status*/ + PSTA,32, + Offset(R_SCS_CFG_PG_CONFIG),/* 0xA2, Device PG config */ + , 2, + PGEN, 1 /* [BIT2] PGE - PG Enable */ + } + + Method (_PS0, 0, Serialized) + { + Store(0, PGEN) /* Disable PG */ + + And(PSTA, 0xFFFFFFFC, PSTA) /* Set BIT[1:0] = 00b - Power State D0 */ + + /* Disable OCP Timer in SCS UFS IOSF Bridge */ + OCPD () + } + + Method (_PS3, 0, Serialized) + { + + Store(1, PGEN) /* Enable PG */ + } + Method (_INI) + { + OCPD () + } + } +} diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig index 6b5f49e..192425c 100644 --- a/src/soc/intel/common/block/scs/Kconfig +++ b/src/soc/intel/common/block/scs/Kconfig @@ -19,10 +19,3 @@ help Override the MMC settings after FSP-S. It should be used only when there is no FSP UPDs for certain setting. - -config SOC_INTEL_COMMON_UFS_SUPPORT - bool - default n - help - Enable UFS support. Should be enabled when a particular SoC supports - boot from UFS. diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index aa5f2b5..0b77f5f 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -2,5 +2,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c endif ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_UFS_SUPPORT) += ufs.c romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c diff --git a/src/soc/intel/common/block/scs/ufs.c b/src/soc/intel/common/block/scs/ufs.c deleted file mode 100644 index e70c87b..0000000 --- a/src/soc/intel/common/block/scs/ufs.c +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi_device.h> -#include <acpi/acpigen.h> -#include <acpi/acpigen_pci.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#if CONFIG(HAVE_ACPI_TABLES) -static void ufs_fill_ssdt(const struct device *dev) -{ - struct acpi_dp *dsd; - - const char *scope = acpi_device_scope(dev); - - acpigen_write_scope(scope); - acpigen_write_device("UFS"); - acpigen_write_ADR_pci_device(dev); - acpigen_write_name_string("_DDN", "UFS Controller"); - - dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "ref-clk-freq", CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ); - acpi_dp_write(dsd); - acpigen_write_device_end(); - acpigen_pop_len(); -} -#endif - -static struct device_operations dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = ufs_fill_ssdt, -#endif - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_ADP_UFS, - 0 -}; - -static const struct pci_driver pch_ufs __pci_driver = { - .ops = &dev_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids -};