Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36651 )
Change subject: [WIP] intel/cannonlake: Implement PCIe RP devicetree update ......................................................................
[WIP] intel/cannonlake: Implement PCIe RP devicetree update
This might need updates to devicetrees that are already patched based on assumptions about FSP's behaivior.
Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/soc/intel/cannonlake/chip.c 1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/36651/1
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0ce2f1a..3fd10f8 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -20,6 +20,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> @@ -28,6 +29,19 @@
#include "chip.h"
+static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .offset = 0, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .offset = 8, .count = 8 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .offset = 0, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .offset = 8, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .offset = 16, .count = 8 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -194,6 +208,12 @@ cnl_configure_pads(NULL, 0);
soc_fill_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + pcie_rp_update_devicetree(pch_h_rp_groups); + else + pcie_rp_update_devicetree(pch_lp_rp_groups); }
static void pci_domain_set_resources(struct device *dev)