Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39317 )
Change subject: soc/intel/tigerlake: Enable CNVi Mode ......................................................................
soc/intel/tigerlake: Enable CNVi Mode
Add configs to enable CNVi mode and CNViBtCore.
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39317/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e57abe8..e0ab421 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -208,6 +208,10 @@ /* Enable Pch iSCLK */ uint8_t pch_isclk;
+ /* CNVi */ + uint8_t CnviMode; + uint8_t CnviBtCore; + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0587b88..152257a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -145,6 +145,10 @@ else params->PchLanEnable = dev->enabled;
+ /* CNVi */ + params->CnviMode = config->CnviMode; + params->CnviBtCore = config->CnviBtCore; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;