Hello Patrick Rudolph, HAOUAS Elyes, build bot (Jenkins), Martin Roth, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35348
to look at the new patch set (#10).
Change subject: Rangeley: Fix incorrect BCLK ......................................................................
Rangeley: Fix incorrect BCLK
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. get_fsb and udelay have been fixed to return the correct BCLK for Rangeley.
Signed-off-by: Hannah Williams hannah.williams@dell.com Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f --- M src/cpu/intel/common/fsb.c M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/northbridge/intel/fsp_rangeley/udelay.c 4 files changed, 29 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35348/10