Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46068 )
Change subject: arch/x86/smbios: Populate SMBIOS type 7 with cache information ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@10 PS8, Line 10: Combine L1 Data cache size and : L1 Instruction cache size
I agree that separating L1 D-CACHE and L1 I-CACHE is more accurate. This could be done in next step;
I don't follow. Isn't this what the current code (with this change) does already in the type 7 tables?
What seems missing is the association of the processor (type 4) with the caches (type 7). The specification mentions mentions type 14 tables for such a case (where the simple handles in type 4 don't work out).
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@11 PS8, Line 11: L1 Instruction cache size, and multiply the cache size of L1 and L2 : by the number of cores
For Intel design, each core has its own L1 caches.
I know that but get_number_of_caches() seems rather complex with many cases. And I was wondering if there is any documentation about that or if it's all based on testing?
https://review.coreboot.org/c/coreboot/+/46068/8/src/arch/x86/smbios.c File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/46068/8/src/arch/x86/smbios.c@888 PS8, Line 888: continue; This will stop us calling smbios_write_type7() for level 1 d-cache. So that information will be missing after this change, afaics.