[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add IRQs for LPSS uart

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44260 )

Change subject: soc/intel/tigerlake: Add IRQs for LPSS uart
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soc/intel/tigerlake: Add IRQs for LPSS uart

Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "APCI mode".

Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/tigerlake/include/soc/irq.h
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44260/1

diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index ad70290..f95f9f6 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -9,4 +9,8 @@
 #define PCH_IRQ10	10
 #define PCH_IRQ11	11

+#define LPSS_UART0_IRQ	16
+#define LPSS_UART1_IRQ	17
+#define LPSS_UART2_IRQ	33
+
 #endif /* _SOC_IRQ_H_ */