[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel: Adapt crashlog IP to also support 64-bit

[Subrata Banik (Code Review)]

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pratikkumar V Prajapati, Sowmya Aralguppe, Tarun.

Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email )

Change subject: soc/intel: Adapt crashlog IP to also support 64-bit
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Patch Set 22:

(2 comments)

Patchset:

PS22:
> I think it's fine but I don't know crashlog well enough to be sure.

Thanks Angel

PS22: 
@[e-mail]: can you please check below prints w/ and w/o your CL?

w/o this CL

```
[DEBUG]  m_cpu_crashLog_size : 0x4000 bytes
[DEBUG]  CPU crashLog present.
[DEBUG]  CPU crash data size: 0x4000 bytes in 0x5 region(s).
[DEBUG]  CPU crashlog storage_off asserted
[DEBUG]  CPU crashlog re_arm asserted
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x4000
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x4000
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x4000
```

w/ this CL

```
[DEBUG]  m_cpu_crashLog_size : 0x824C bytes
[DEBUG]  CPU crashLog present.
[DEBUG]  CPU crash data size: 0x824C bytes in 0x5 region(s).
[DEBUG]  CPU crashlog storage_off asserted
[DEBUG]  CPU crashlog re_arm asserted
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x824c
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x824c
[DEBUG]  crashlog size:pmc-0x1050, cpu-0x824c
```

I felt the CPU crashlog size is always higher with your CL.