[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63954 )

Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
......................................................................

soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done

This patch calls into the PMC IPC function that informs about PMC
enumeration.

Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC
IPC, hence, this patch is considered as an improvement over FSP Notify
Phase API.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS without any PMC IPC
error.

Signed-off-by: Subrata Banik 
Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Angel Pons 
Reviewed-by: Lean Sheng Tan 
---
M src/soc/intel/alderlake/lockdown.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Lean Sheng Tan: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
index d926dbb..c291e34 100644
--- a/src/soc/intel/alderlake/lockdown.c
+++ b/src/soc/intel/alderlake/lockdown.c
@@ -9,6 +9,7 @@
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelpch/lockdown.h>
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
@@ -36,6 +37,9 @@
    	setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
    				 PM_CFG_XRAM_READ_DISABLE);
    }
+
+	/* Send PMC IPC to inform about PCI enumeration done */
+	pmc_send_pci_enum_done();
 }

static void pch_lockdown_cfg(void)