[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/jasperlake: Enable early caching of RAMTOP region

[Matt DeVillier (Code Review)]

Attention is currently required from: Sean Rhodes, Subrata Banik.

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74518 )

Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74518/comment/f70f1fd7_ceb3e553 
PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of
            : 16MB)
same Q as with CML, how does this affect boards with a 32MB flash?