[coreboot-gerrit] Change in coreboot[master]: AGESA, binaryPI: implement C bootblock

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )

Change subject: AGESA, binaryPI: implement C bootblock
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Patch Set 30:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
File src/drivers/amd/agesa/bootblock.c:

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
PS28, Line 40: 	set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
> Looped through all BKDGS for fam14h, fam15h and 16h until processors 30-3f. […]

Two quick questions. I see in the CPU init procedures that siblings are handled separately with rdmsr_amd and wrmsr_amd instruction which seem to have weird value in EDX 0x9c5a203a. What is the purpose of these functions? Could it fix the issue with duplicates?