Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37027 )
Change subject: sb/intel/spi: Drop CAR_GLOBAL_MIGRATION ......................................................................
sb/intel/spi: Drop CAR_GLOBAL_MIGRATION
Change-Id: I693cf494522c3bc1e1697a09be3e98fcb6db634d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c 1 file changed, 90 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/37027/1
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0df..96322e42d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -16,7 +16,6 @@ */
/* This file is derived from the flashrom project. */ -#include <arch/early_variables.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -110,7 +109,7 @@ uint8_t fpr_max; };
-static struct ich_spi_controller g_cntlr CAR_GLOBAL; +static struct ich_spi_controller g_cntlr;
enum { SPIS_SCIP = 0x0001, @@ -255,14 +254,13 @@
static void ich_set_bbar(uint32_t minaddr) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar;
minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; + ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr->bbar); + writel_(ichspi_bbar, g_cntlr.bbar); }
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) @@ -273,7 +271,6 @@
void spi_init(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; @@ -292,42 +289,42 @@ rcrb = (uint8_t *)(rcba & 0xffffc000); if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); - cntlr->ich7_spi = ich7_spi; - cntlr->opmenu = ich7_spi->opmenu; - cntlr->menubytes = sizeof(ich7_spi->opmenu); - cntlr->optype = &ich7_spi->optype; - cntlr->addr = &ich7_spi->spia; - cntlr->data = (uint8_t *)ich7_spi->spid; - cntlr->databytes = sizeof(ich7_spi->spid); - cntlr->status = (uint8_t *)&ich7_spi->spis; - cntlr->control = &ich7_spi->spic; - cntlr->bbar = &ich7_spi->bbar; - cntlr->preop = &ich7_spi->preop; - cntlr->fpr = &ich7_spi->pbr[0]; - cntlr->fpr_max = 3; + g_cntlr.ich7_spi = ich7_spi; + g_cntlr.opmenu = ich7_spi->opmenu; + g_cntlr.menubytes = sizeof(ich7_spi->opmenu); + g_cntlr.optype = &ich7_spi->optype; + g_cntlr.addr = &ich7_spi->spia; + g_cntlr.data = (uint8_t *)ich7_spi->spid; + g_cntlr.databytes = sizeof(ich7_spi->spid); + g_cntlr.status = (uint8_t *)&ich7_spi->spis; + g_cntlr.control = &ich7_spi->spic; + g_cntlr.bbar = &ich7_spi->bbar; + g_cntlr.preop = &ich7_spi->preop; + g_cntlr.fpr = &ich7_spi->pbr[0]; + g_cntlr.fpr_max = 3; } else { ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); - cntlr->ich9_spi = ich9_spi; + g_cntlr.ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); - cntlr->hsfs = hsfs; - cntlr->opmenu = ich9_spi->opmenu; - cntlr->menubytes = sizeof(ich9_spi->opmenu); - cntlr->optype = &ich9_spi->optype; - cntlr->addr = &ich9_spi->faddr; - cntlr->data = (uint8_t *)ich9_spi->fdata; - cntlr->databytes = sizeof(ich9_spi->fdata); - cntlr->status = &ich9_spi->ssfs; - cntlr->control = (uint16_t *)ich9_spi->ssfc; - cntlr->bbar = &ich9_spi->bbar; - cntlr->preop = &ich9_spi->preop; - cntlr->fpr = &ich9_spi->pr[0]; - cntlr->fpr_max = 5; + g_cntlr.hsfs = hsfs; + g_cntlr.opmenu = ich9_spi->opmenu; + g_cntlr.menubytes = sizeof(ich9_spi->opmenu); + g_cntlr.optype = &ich9_spi->optype; + g_cntlr.addr = &ich9_spi->faddr; + g_cntlr.data = (uint8_t *)ich9_spi->fdata; + g_cntlr.databytes = sizeof(ich9_spi->fdata); + g_cntlr.status = &ich9_spi->ssfs; + g_cntlr.control = (uint16_t *)ich9_spi->ssfc; + g_cntlr.bbar = &ich9_spi->bbar; + g_cntlr.preop = &ich9_spi->preop; + g_cntlr.fpr = &ich9_spi->pr[0]; + g_cntlr.fpr_max = 5;
- if (cntlr->hsfs & HSFS_FDV) { + if (g_cntlr.hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); - cntlr->flmap0 = readl_(&ich9_spi->fdod); + g_cntlr.flmap0 = readl_(&ich9_spi->fdod); writel_(0x1000, &ich9_spi->fdoc); - cntlr->flcomp = readl_(&ich9_spi->fdod); + g_cntlr.flcomp = readl_(&ich9_spi->fdod); } }
@@ -344,9 +341,9 @@ { struct ich_spi_controller *cntlr = &g_cntlr; if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN); + return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN); } else { - return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN); + return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN); } }
@@ -415,7 +412,6 @@
static int spi_setup_opcode(spi_transaction *trans) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; uint8_t opmenu[MENU_BYTES];
@@ -423,10 +419,10 @@ spi_use_out(trans, 1); if (!spi_locked()) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr->opmenu); - optypes = readw_(cntlr->optype); + writeb_(trans->opcode, g_cntlr.opmenu); + optypes = readw_(g_cntlr.optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr->optype); + writew_(optypes, g_cntlr.optype); return 0; }
@@ -438,7 +434,7 @@ if (trans->opcode == SPI_OPCODE_WREN) return 0;
- read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu)); for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; @@ -450,7 +446,7 @@ return -1; }
- optypes = readw_(cntlr->optype); + optypes = readw_(g_cntlr.optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -495,15 +491,14 @@ */ static int ich_status_poll(u16 bitmask, int wait_til_set) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0;
while (timeout--) { - status = readw_(cntlr->status); + status = readw_(g_cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr->status); + writew_((status & bitmask), g_cntlr.status); return status; } udelay(10); @@ -516,16 +511,14 @@
static int spi_is_multichip(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - if (!(cntlr->hsfs & HSFS_FDV)) + if (!(g_cntlr.hsfs & HSFS_FDV)) return 0; - return !!((cntlr->flmap0 >> 8) & 3); + return !!((g_cntlr.flmap0 >> 8) & 3); }
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -551,7 +544,7 @@ if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1;
- writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); + writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status);
spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -566,7 +559,7 @@ * issuing a transaction between WREN and DATA. */ if (!spi_locked()) - writew_(trans.opcode, cntlr->preop); + writew_(trans.opcode, g_cntlr.preop); return 0; }
@@ -574,13 +567,13 @@ control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
/* Issue atomic preop cycle if needed */ - if (readw_(cntlr->preop)) + if (readw_(g_cntlr.preop)) control |= SPIC_ACS;
if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
/* * This is a 'no data' command (like Write Enable), its @@ -588,7 +581,7 @@ * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr->control); + writew_(control, g_cntlr.control);
/* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -610,7 +603,7 @@ * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr->databytes) { + if (trans.bytesout > g_cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -624,28 +617,28 @@ uint32_t data_length;
/* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); + writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
if (trans.bytesout) - data_length = min(trans.bytesout, cntlr->databytes); + data_length = min(trans.bytesout, g_cntlr.databytes); else - data_length = min(trans.bytesin, cntlr->databytes); + data_length = min(trans.bytesin, g_cntlr.databytes);
/* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr->data, data_length); + write_reg(trans.out, g_cntlr.data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; }
/* Add proper control fields' values */ - control &= ~((cntlr->databytes - 1) << 8); + control &= ~((g_cntlr.databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8;
/* write it */ - writew_(control, cntlr->control); + writew_(control, g_cntlr.control);
/* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -658,7 +651,7 @@ }
if (trans.bytesin) { - read_reg(cntlr->data, trans.in, data_length); + read_reg(g_cntlr.data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -667,7 +660,7 @@
spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr->preop); + writew_(0, g_cntlr.preop);
return 0; } @@ -675,10 +668,9 @@ /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; + uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
- writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); + writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr); }
/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -688,22 +680,21 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfs; uint32_t addr;
timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & + while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
if (!timeout) { uint16_t hsfc; - addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr->ich9_spi->hsfc); + addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -713,8 +704,8 @@
if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr->ich9_spi->hsfc); + addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -728,7 +719,6 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start, end, erase_size; int ret; uint16_t hsfc; @@ -751,17 +741,17 @@
while (offset < end) { /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
ich_hwseq_set_addr(offset);
offset += erase_size;
- hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; @@ -778,13 +768,12 @@
static void ich_read_data(uint8_t *data, int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int i; uint32_t temp32 = 0;
for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(cntlr->data + i); + temp32 = readl_(g_cntlr.data + i);
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } @@ -793,7 +782,6 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -807,20 +795,20 @@ }
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
while (len > 0) { - block_len = min(len, cntlr->databytes); + block_len = min(len, g_cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); - hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; @@ -839,7 +827,6 @@ */ static void ich_fill_data(const uint8_t *data, int len) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t temp32 = 0; int i;
@@ -853,17 +840,16 @@ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, cntlr->data + (i - (i % 4))); + writel_(temp32, g_cntlr.data + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, cntlr->data + (i - (i % 4))); + writel_(temp32, g_cntlr.data + (i - (i % 4))); }
static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -877,24 +863,24 @@ }
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); + writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
while (len > 0) { - block_len = min(len, cntlr->databytes); + block_len = min(len, g_cntlr.databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1;
ich_hwseq_set_addr(addr);
ich_fill_data(buf, block_len); - hsfc = readw_(&cntlr->ich9_spi->hsfc); + hsfc = readw_(&g_cntlr.ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr->ich9_spi->hsfc); + writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { printk(BIOS_ERR, "SF: write failure at %x\n", @@ -919,7 +905,6 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); @@ -932,7 +917,7 @@ flash->name = "Opaque HW-sequencing";
ich_hwseq_set_addr(0); - switch ((cntlr->hsfs >> 3) & 3) { + switch ((g_cntlr.hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -947,12 +932,12 @@ break; }
- flash->size = 1 << (19 + (cntlr->flcomp & 7)); + flash->size = 1 << (19 + (g_cntlr.flcomp & 7));
flash->ops = &spi_flash_ops;
- if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) - flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); + if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3)) + flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7)); printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
return 0; @@ -999,7 +984,6 @@ const struct region *region, const enum ctrlr_prot_type type) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start = region_offset(region); u32 end = start + region_sz(region) - 1; u32 reg; @@ -1007,16 +991,16 @@ int fpr; uint32_t *fpr_base;
- fpr_base = cntlr->fpr; + fpr_base = g_cntlr.fpr;
/* Find first empty FPR */ - for (fpr = 0; fpr < cntlr->fpr_max; fpr++) { + for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) { reg = read32(&fpr_base[fpr]); if (reg == 0) break; }
- if (fpr == cntlr->fpr_max) { + if (fpr == g_cntlr.fpr_max) { printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); return -1; } @@ -1057,7 +1041,6 @@
void spi_finalize_ops(void) { - struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u16 spi_opprefix; u16 optype = 0; struct intel_swseq_spi_config spi_config_default = { @@ -1106,12 +1089,12 @@
spi_opprefix = spi_config->opprefixes[0] | (spi_config->opprefixes[1] << 8); - writew_(spi_opprefix, cntlr->preop); + writew_(spi_opprefix, g_cntlr.preop); for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { optype |= (spi_config->ops[i].type & 3) << (i * 2); - writeb_(spi_config->ops[i].op, &cntlr->opmenu[i]); + writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]); } - writew_(optype, cntlr->optype); + writew_(optype, g_cntlr.optype); }
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)