Hello Patrick Rudolph, Subrata Banik, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32155
to look at the new patch set (#2).
Change subject: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE. ......................................................................
src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE.
When VBOOT Stage Verification is enabled, FSP_S component needs to be verified. This logic has been added.
TEST=Create a coreboot.rom image by enabling CONFIG_VBOOT and CONFIG_VBOOT_STAGE_VERIFICATION. Verify that the image boots to authenticated payload and graphics is displayed via HDMI and Display Port.
Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d Signed-off-by: Sukerkar, Amol N amol.n.sukerkar@intel.com --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 35 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32155/2